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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer description the 7480/7481 group is the single-chip microcomputer adopting the silicon gate cmos process. in addition to its simple instruction set, the rom, ram, and i/o addresses are placed in the same memory space. having built-in serial i/o, a-d converter, and watchdog timer, this single-chip microcomputer is useful for control of automobiles, of- fice automation equipment and home electric appliances. the 7480/7481 group includes multiple types which differ in the memory type, size, and package. features l number of basic machine language instructions ..................... 71 l minimum instruction execution time ................................... 0.5 s (at 8 mhz clock input oscillation frequency) l memory size rom ........................................... 4 k to 16 k bytes ram ............................................ 128 to 448 bytes l programmable i/o ports .................................... 18 (7480 group) (p0, p1, p4, p5) 24 (7481 group) l input ports ............................................................ 8 (7480 group) (p2, p3) 12 (7481 group) l built-in programmable pull-up transistors (p0, p1) l built-in clamp diodes ............................................ 2 (7480 group) (p4, p5) 8 (7481 group) l interrupt ................................................... 14 sources, 13 vectors l timer x, y ..................................................................... 16-bit 5 2 l timer 1, 2 ....................................................................... 8-bit 5 2 l serial i/o ....................... 8-bit x 1 (uart or clock-synchronized) l a-d converter ............................ 8-bit x 4 channels (7480 group) 8-bit x 8 channels (7481 group) l built-in watchdog timer l power source voltage ................................................ 2.7 to 4.5 v (at [2.2 v cc -2] mhz clock input oscillation frequency) 4.5 to 5.5 v (at 8 mhz clock input oscillation frequency) l power dissipation .............................................................. 35 mw (at 8 mhz clock input oscillation frequency and 5 v power source voltage) applications automobiles, office automation equipment, home electric appli- ances, etc. fig. 1 pin configuration (top view) preliminar y notice: this is not a final specification. some parametric limits are subject to change. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m37480mx-xxxsp m37480mxt-xxxsp m37480e8-xxxsp m37480e8t-xxxsp p1 7 /s rdy p1 6 /s clk p1 5 /t x d p1 4 /r x d p1 3 /t 1 p1 2 /t 0 p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 /cntr 1 p4 0 /cntr 0 p3 3 p3 2 p3 1 /int 1 p3 0 /int 0 reset v cc outline 32p4b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m37480mx-xxxfp m37480mxt-xxxfp m37480e8-xxxfp m37480e8t-xxxfp p1 7 /s rdy p1 6 /s clk p1 5 /t x d p1 4 /r x d p1 3 /t 1 p1 2 /t 0 p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 /cntr 1 p4 0 /cntr 0 p3 3 p3 2 p3 1 /int 1 p3 0 /int 0 reset v cc outline 32p2w-a pin configuration
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 2 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 2 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 26 25 24 23 27 33 35 36 37 38 39 40 41 42 34 43 44 p1 3 /t 1 p1 2 /t 0 p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p2 0 /in 0 v ref x in x out v ss av ss p3 0 /int 0 v cc p5 1 p5 0 reset p0 3 p0 2 p0 1 p0 0 p4 1 /cntr 1 p4 0 /cntr 2 p3 3 p3 2 p3 1 /int 1 p4 3 p4 2 p1 7 /s rdy p0 7 p0 6 p0 5 p0 4 p5 2 p1 6 /s clk p1 5 /t x d p1 4 /r x d p5 3 v ss m37481mx-xxxfp m37481mxt-xxxfp m37481e8-xxxfp m37481e8t-xxxfp outline 44p6n-a 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 28 29 30 31 32 m37481mx-xxxsp m37481mxt-xxxsp m37481e8-xxxsp m37481e8t-xxxsp m37481e8ss p1 7 /s rdy p1 6 /s clk p1 5 /t x d p1 4 /r x d p1 3 /t 1 p1 2 /t 0 p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 /cntr 1 p4 0 /cntr 0 p3 3 p3 2 p3 1 /int 1 p3 0 /int 0 reset v cc 17 26 25 24 23 22 18 19 20 21 27 33 35 36 37 38 39 40 41 42 34 p5 3 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p5 2 p5 1 p5 0 p4 3 p4 2 outline 42p4b 42s1b-a
3 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. 7480/7481 group product list table 1. 7480/7481 group product list ram (bytes) rom (bytes) remarks m37480m2t-xxxsp m37480m2t-xxxfp m37480m4-xxxsp m37480m4-xxxfp m37480m4t-xxxsp m37480m4t-xxxfp m37480m8-xxxsp m37480m8-xxxfp m37480m8t-xxxsp m37480m8t-xxxfp m37480e8sp m37480e8fp m37480e8-xxxsp m37480e8-xxxfp m37480e8t-xxxsp m37480e8t-xxxfp m37481m2t-xxxsp m37481m2t-xxxfp m37481m4-xxxsp m37481m4-xxxfp m37481m4t-xxxsp m37481m4t-xxxfp m37481m8-xxxsp m37481m8-xxxfp m37481m8t-xxxsp m37481m8t-xxxfp m37481e8sp m37481e8fp m37481e8-xxxsp m37481e8-xxxfp m37481e8t-xxxsp m37481e8t-xxxfp m37481e8ss product model name package mask rom version* mask rom version mask rom version* mask rom version mask rom version* one time prom version (shipped in blank) one time prom version one time prom version* mask rom version* mask rom version mask rom version* mask rom version mask rom version* one time prom version (shipped in blank) one time prom version one time prom version* built-in eprom version 128 256 448 128 256 448 4096 8192 16384 4096 8192 16384 32p4b 32p2w-a 32p4b 32p2w-a 32p4b 32p2w-a 32p4b 32p2w-a 32p4b 32p2w-a 32p4b 32p2w-a 32p4b 32p2w-a 32p4b 32p2w-a 42p4b 44p6n-a 42p4b 44p6n-a 42p4b 44p6n-a 42p4b 44p6n-a 42p4b 44p6n-a 42p4b 44p6n-a 42p4b 44p6n-a 42p4b 44p6n-a 42s1b-a *: extended operating temperature range version i/o port 18 i/o ports 8 input ports (including 4 analog input ports) 24 i/o ports 12 input ports (including 8 analog input ports)
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 4 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 3 rom/ram development schedule note: regarding the models being developed and planned, the development schedule may be reviewed. in case of the models be- ing planned, the development of them may be stopped. 7480/7481 group rom/ram development schedule rom size (bytes) 16k 12k 8k 4k 128 256 384 448 0 m37480m2t-xxxsp/fp m37481m2t-xxxsp/fp m37480m4-xxxsp/fp m37480m4t-xxxsp/fp m37481m4-xxxsp/fp m37481m4t-xxxsp/fp m37480m8/e8-xxxsp/fp m37481m8/e8-xxxsp/fp m37481e8ss m37480m8t/e8t-xxxsp/fp m37481m8t/e8t-xxxsp/fp : being developed : being planned ram size (bytes)
5 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 4 function block diagram (1) 24 23 22 19 13 9 10 11 12 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 14 15 18 17 16 p4 (2) p2 (4) p1 (8) a-d converter p0 (8) serial i/o (8) clock generating circuit ram 448 bytes program counter pc h (8) program counter pc l (8) rom 16384 bytes accumulator a (8) index register x (8) index register y (8) stack pointer s (8) processor status register ps (8) timer 1 (8) timer 2 (8) timer x (16) timer y (16) instruction decoder control signal v cc v ss reset input clock output x out clock input x in (note 2) data bus (note 1) 8-bit arithmetic and logical unit p3 (4) cntr 1 cntr 0 int 1 int 0 4 m37480m8/e8-xxxsp/fp, m37480m8t/e8t-xxxsp/fp function block diagram i/o port p4 input port p3 v ref reference voltage input input port p2 i/o port p1 i/o port p0 notes 1: 8192 bytes for m37480m4-xxxsp/fp, m37480m4t-xxxsp/fp and 4096 bytes for m37480m2t-xxxsp/fp 2: 256 bytes for m37480m4-xxxsp/fp, m37480m4t-xxxsp/fp and 128 bytes for m37480m2t-xxxsp/fp reset instruction register (8) int 1 int 0 2021 functional block diagram
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 6 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 5 function block diagram (2) 1 42 24 23 33 32 31 30 29 26 18 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 19 20 25 22 21 p5 (4) p4 (4) p 2 (8) p1 (8) a-d converter p0 (8) serial i/o (8) clock generating circuit ram 448 bytes program counter pc h (8) program counter pc l (8) rom 16384 bytes accumulator a (8) index register x (8) index register y (8) stack pointer s (8) processor status register ps (8) timer 1 (8) timer 2 (8) timer x (16) timer y (16) instruction decoder control signal v cc v ss reset input clock output x out clock input x in (note 2) data bus (note 1) 8-bit arithmetic and logical unit p3 (4) cntr 1 cntr 0 int 1 int 0 8 m37481m8/e8-xxxsp, m37481m8t/e8t-xxxsp, m37481e8ss function block diagram i/o port p5 i/o port p4 input port p3 v ref reference voltage input input port p2 i/o port p1 i/o port p0 notes 1: 8192 bytes for m37481m4-xxxsp, m37481m4t-xxxsp and 4096 bytes for m37481m2t-xxxsp 2: 256 bytes for m37481m4-xxxsp, m37481m4t-xxxsp and 128 bytes for m37481m2t-xxxsp reset instruction register (8) int 1 int 0 2728
7 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 6 function block diagram (3) 40 38 20 19 29 28 27 26 25 24 22 13 5 6 7 8 9 10 11 12 41 42 43 44 1 2 3 4 37 36 35 34 33 32 31 30 14 15 21 18 17 p5 (4) p4 (4) p2 (8) p1 (8) a-d converter p0 (8) serial i/o (8) clock generating circuit ram 448 bytes program counter pc h (8) program counter pc l (8) rom 16384 bytes accumulator a (8) index register x (8) index register y (8) stack pointer s (8) processor status register ps (8) timer 1 (8) timer 2 (8) timer x (16) timer y (16) instruction decoder control signal v cc v ss reset input clock output x out clock input x in (note 2) data bus (note 1) 8-bit arithmetic and logical unit p3 (4) cntr 1 cntr 0 int 1 int 0 8 m37481m8/e8-xxxfp, m37481m8t/e8t-xxxfp function block diagram i/o port p5 i/o port p4 input port p3 v ref reference voltage input input port p2 i/o port p1 i/o port p0 notes 1: 8192 bytes for m37481m4-xxxfp, m37481m4t-xxxfp and 4096 bytes for m37481m2t-xxxfp 2: 256 bytes for m37481m4-xxxfp, m37481m4t-xxxfp and 128 bytes for m37481m2t-xxxfp reset instruction register (8) 16 av ss 39 int 1 int 0 23
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 8 preliminar y notice: this is not a final specification. some parametric limits are subject to change. number of basic instructions instruction execution time clock input oscillation frequency serial i/o timers subroutine nesting interrupt 71 (740 family 69 basic instructions + 2 multiplication/division instructions) 0.5 s (minimum instructions, at 8 mhz clock input oscillation frequency) 8 mhz (max.) 16384 bytes 8192 bytes 4096 bytes 448 bytes 256 bytes 128 bytes 8 bits 5 2 4 bits 5 1 5 v C5 to 10 ma (p0, p1: cmos tri-states), 10 ma (p4, p5: n channel) 8 bits 5 1 16-bit timer x 2, 8-bit timer x 2 192 max. 96 max. 64 max. 5 external interrupts, 8 internal interrupts, 1 software interrupt built-in circuit with feedback resistor (with external ceramic oscillator) built-in circuit 2.7 to 4.5 v (at f(x in ) = (2.2v cc C 2) mhz) 4.5 to 5.5 v (at f(x in )=8 mhz) 35 mw (standard, at 8 mhz clock input oscillation frequency) C20 to 85 c (C40 to 85 c for extended operating temperature range version) cmos silicon gate 8 bits 5 1 4 bits 5 1 4 bits 5 1 4 bits 5 1 2 bits 5 1 functions of 7480/7481 group table 2. functions of 7480/7481 group 8 bits 5 4 analog inputs (in common with p2) 8 bits 5 8 analog inputs (in common with p2) 42-pin sdip/44-pin ofp32-pin sdip/32-pin sop functions m37480m4/m8/e8-xxxsp/fp m37480m2t/m4t/m8t/e8t-xxxsp/fp m37481m4/m8/e8-xxxsp/fp m37481m2t/m4t/m8t/e8t-xxxsp/fp i/o input input i/o i/o m8/e8 m4 m2 i/o withstand voltage output current memory size i/o port i/o characteristics m8/e8 m4 m2 m8/e8 m4 m2 p0, p1 p2 p3 p4 p5 rom ram parameter a-d converter (successive comparison method) clock generating circuit watchdog timer power source voltage power dissipation operating temperature range device structure package
9 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. v cc , v ss av ss v ref _____ reset p0 0 C p0 7 p1 0 C p1 7 pin description table 3. pin description clock input clock output x in x out input output input input i/o i/o power source analog power source input reference voltage input reset input i/o port p0 i/o port p1 p2 0 C p2 7 apply a voltage of 2.7 to 5.5 v to v cc and 0 v to v ss . ground level input pin for a-d converter. apply the same voltage as vss. (this pin is for 44p6n-a package only.) reference voltage input pin for a-d converter. (when the a-d converter is not used, connect it to v cc .) reset input pin active l. these are i/o pins for the internal clock generating circuit of the main clock. to control the generating frequency, an external ceramic is connected between the x in and x out pins. if an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. the feedback resistor is connected between x in and x out . 8-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistors can be connected in units of 1 bit, and a key-on wake-up function is provided. 8-bit i/o port. the output structure is cmos output. when this port is selected for input, pull-up transistors can be connected in units of 4 bits. p1 2 and p1 3 are in common with timer output pins t 0 and t 1 . p1 4 , p1 5 , p1 6 and p1 7 are in common with serial i/o pins r x d, t x d, s clk and ____ s rdy , respectively. 8-bit input port. (only 4 bits of p2 0 to p2 3 for the 7480 group) or analog input pins in 0 to in 7 (in 0 to in 3 for the 7480 group). input port p2 input 4-bit input port. p3 0 and p3 1 can be configured to serve as external interrupt input pins int 0 and int 1 . 4-bit i/o port. (2 bits of p4 0 and p4 1 for the 7480 group). the output structure is n-channel open drain output, having a built-in clamp diode. p4 0 and p4 1 can be configured to serve as timer i/o pins cntr 0 and cntr 1 . 4-bit i/o port. (this port is not included in the 7480 group.) the output structure is n-channel open drain output, having built-in clamp diodes. p3 0 C p3 3 input port p3 p4 0 C p4 3 p5 0 C p5 3 i/o port p4 i/o port p5 i/o i/o input pin name functions input/ output
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 10 preliminar y notice: this is not a final specification. some parametric limits are subject to change. cpu mode register the stack page selection bit is assigned to the cpu mode regis- ter. this register is allocated at address 00fb 16 . fig. 7 structure of cpu mode register functional description central processing unit (cpu) the 7480/7481 group uses the standard 740 family cpu. refer to the table of 740 family addressing modes and machine instruc- tions or the melps 740 programming manual for details on the instruction set. machine-resident 740 family instructions are as follows: 1. the fst and slw instructions are not available. 2. the mul and div instructions are available. 3. the wit instruction is available. (note) 4. the stp instruction is available. (note) note: when using these instructions, refer to the corresponding chapter stp and wit instruction control below. cpu mode register (cpum: address 00fb 16 ) b7 b0 stack page selection bit (note) 0 : page 0 1 : page 1 system clock division proportion selection bit 0 : f = f(x in )/2 (high-speed mode) 1 : f = f(x in )/8 (medium-speed mode) not used. these bits must always be set to 0. watchdog timer l count source selection bit 0 : f(x in )/8 1 : f(x in )/16 note : in the models of ram size under 192 bytes, set this bit to 0. not used (undefined at read) not used (undefined at read)
11 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. memory ? sfr area this sfr area is provided in the zero page and contains the reg- isters for controlling i/o ports and timers. ? ram ram is used for data storage and for calling subroutines, as well as for a stack area for interrupts. ? rom rom is used for storing user programs and interrupt vectors. fig. 8 memory map ? interrupt vector area the interrupt vector area is used for storing vector addresses when an interrupt is generated or at reset. ? zero page this area can be accessed with 2 words when the zero page ad- dressing mode is used. ? special page this area can be accessed with 2 words when the special page addressing mode is used. sfr area not used interrupt vector area 0000 16 007f 16 0080 16 00bf 16 00c0 16 00ff 16 0100 16 013f 16 01ff 16 c000 16 e000 16 f000 16 ff00 16 ffe4 16 ffff 16 zero page special page ram (192 bytes) for m37480m4, m37480m8/e8, m37481m4, m37481m8/e8 ram (128 bytes) for m37480m2, m37481m2 ram (256 bytes) for m37480m8/e8, m37481m8/e8 ram (64 bytes) for m37480m4, m37481m4 rom (16384 bytes) for m37480m8/e8, m37481m8/e8 rom (8192 bytes) for m37480m4, m37481m4 rom (4096 bytes) for m37480m2, m37481m2
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 12 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 9 sfr (special function register) memory map note: this port is not allocated in the 7480 group. 00c0 16 00c1 16 00c2 16 00c3 16 00c4 16 00c5 16 00c6 16 00c7 16 00c9 16 00c9 16 00ca 16 00cb 16 00cc 16 00cd 16 00ce 16 00cf 16 00d0 16 00d1 16 00d2 16 00d3 16 00d4 16 00d5 16 00d6 16 00d7 16 00d8 16 00d9 16 00da 16 00db 16 00dc 16 00dd 16 00de 16 00df 16 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 00e9 16 00ea 16 00eb 16 00ec 16 00ed 16 00ee 16 00ef 16 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 00f6 16 00f7 16 00f8 16 00f9 16 00fa 16 00fb 16 00fc 16 00fd 16 00fe 16 00ff 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) (note) edge polarity selection register (eg) a-d control register (adcon) a-d conversion register (ad) stp instruction operation control register (stpcon) port p5 direction register (p5d) (note) port p0 pull-up control register (p0pcon) port p1 pull-up control register (p1pcon) port p4p5 input control register (p4p5con) transmit/receive buffer register (tb/rb) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) baud rate generator (brg) bus collision detection control register (busarbcon) watchdog timer h (wdth) timer x low-order (txl) timer x high-order (txh) timer y low-order (tyl) timer y high-order (tyh) timer 1 (t1) timer 2 (t2) timer x mode register (txm) timer y mode register (tym) timer xy control register (txycon) timer 1 mode register (t1m) timer 2 mode register (t2m) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2)
13 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. [pull-up control registers] ports p0 and p1 are provided with a programmable pull-up tran- sistor. when 1 is written to the pull-up control register and the direction register is in the input mode, the pull-up transistor turns on, and the port is pulled up. n notes on use for stp instruction when the 7480/7481 group is executing an stp instruction, apply 0 v or the same voltage as vcc to the following pins. if an intermediate voltage is applied to these pins, a through-cur- rent flows to the input gates and the power current increases. p4, p5, p3, p1 6 , p1 4 [port p4p5 input control register] when ports p4 2 , p4 3 and p5 of the 7481 group are selected for in- put, clear the corresponding direction register to 0 and set 1 to the corresponding bit of the port p4p5 input control register. ports p4 2 , p4 3 and p5 are not included in the 7480 group. fix each bit of the port p4p5 input control register to 0. fig. 10 structure of pull-up control register i/o ports [direction registers] the i/o ports have direction registers which determine the input/ output direction of each pin in units of bit. when a bit of the direc- tion register is set to 1, the corresponding pin becomes an output port. when the bit is cleared to 0, it becomes an input port. if data is read from a pin configured as output, the value of the port latch is read rather than the value of this pin. a pin configured as input becomes floating and its value can be read. if data is written to a pin, it is written to the port latch, but the pin remains floating. fig. 11 structure of port p4p5 input control register port p4p5 input control register (p4p5con : address 00d2 16 ) p4 2 , p4 3 input control bit p5 input control bit (for the 7480 group) set this bit to 0. (for the 7481 group) set this bit to 1. b7 b0 not used (0 at read) port p1 pull-up control register (p1pcon : address 00d1 16 ) p1 3 C p1 0 pull-up control bit p1 7 C p1 4 pull-up control bit b7 b0 port p0 pull-up control register (p0pcon : address 00d0 16 ) p0 0 pull-up control bit p0 1 pull-up control bit p0 2 pull-up control bit p0 3 pull-up control bit p0 4 pull-up control bit p0 5 pull-up control bit p0 6 pull-up control bit p0 7 pull-up control bit b7 b0 0 : pull-up transistor off 1 : pull-up transistor on 0 : pull-up transistor off 1 : pull-up transistor on not used (undefined at read)
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 14 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 12 block diagram of ports (1) direction register port latch interrupt control circuit tr1 port p0 data bus port p0 tr2 port p1 3 data bus t2m 1 t 1 data bus tr3 port p1 2 data bus t1m 1 t 0 port p1 1 tr4 data bus tr5 data bus port p1 0 ports p1 0 C p1 3 tr1 to tr5 are pull-up transistors. pull-up control register port latch pull-up control register port latch port latch port latch direction register direction register direction register direction register
15 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 13 block diagram of ports (2) direction register port latch tr6 port p1 7 data bus sioe siom srdy s rdy tr7 port p1 6 data bus siom sioe s clk output scs sioe tr8 port p1 5 data bus sioe t x d te tr9 port p1 4 data bus sioe re r x d data bus tr6 to tr9 are pull-up transistors. ports p1 4 C p1 7 s clk input direction register port latch direction register port latch direction register port latch pull-up control register
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 16 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 14 block diagram of ports (3) data bus multi- plexer port p2 a-d conversion circuit port p2 port p3 int 0 , int 1 data bus port p3 data bus port p4 0 , p4 1 cntr 0 , cntr 1 input port p4 2 , p4 3, p5 0 , p5 1, p5 2 , p5 3 data bus port p4 2 , p4 3, p5 0 , p5 1, p5 2 , p5 3 timer output timer x,y operating mode bits 001 100 101 110 port p4 p5 input control register (for the 7480 group) set this bit to 0. (for the 7481 group) set this bit to 1. port p4 0 , p4 1 direction register port latch direction register port latch
17 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. interrupts interrupts are vectored interrupts, and they can be caused by 14 different sources: 5 external sources, 8 internal sources, and 1 software source. (1) interrupt control all interrupts, except the brk instruction interrupt, have an inter- rupt request bit and an interrupt enable bit. additionally, a global interrupt disable flag affects them. when the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is ac- cepted. the interrupt request bits can be cleared by the program but can- not be set. the interrupt enable bit can be set and cleared by the program. the reset and brk instruction interrupt can never be disabled. other interrupts are disabled when the interrupt disable flag is set. (2) interrupt operation when an interrupt request is accepted: 1. the contents of the program counter and the processor status register are automatically pushed into the stack. 2. the interrupt disable flag is set and the interrupt request bit is cleared. 3. the interrupt jump destination address is read into the program counter. n notes ? when the active edge of an external interrupt (int 0 , int 1 , cntr 0 , cntr 1 ) is set, the interrupt request bit may also be set. therefore, disable the external interrupt and set the edge polar- ity selection register. then clear the interrupt request bit and accept the external interrupt. ? input a trigger width over 250 ns to the int 0 /int 1 pin.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 18 preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 4. interrupt vector addresses and priority at reset at detection of either rising edge or falling edge of int 0 input at detection of either rising edge or falling edge of int 1 input at input l to port p0 in key-on wake-up mode at detection of either rising edge or falling edge of cntr 0 input at detection of either rising edge or falling edge of cntr 1 input at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at completion of serial i/o data reception at completion of serial i/o transfer shift or when transmission buffer is empty at detection of bus collision at completion of a-d conversion at execution of brk instruction non-maskable external interrupt (active edge programmable) external interrupt (active edge programmable) validity after execution of stp/wit instruction external interrupt (active edge programmable) external interrupt (active edge programmable) non-maskable software interrupt reset (note 2) int 0 int 1 key-on wake-up cntr 0 cntr 1 timer x timer y timer 1 timer 2 serial i/o reception serial i/o transmission bus arbitration a-d conversion brk instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 interrupt source prior- ity vector address (note 1) high-order low-order interrupt request generating conditions remarks ffff 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 fffe 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset is mentioned in the table because its operation is the same as an interrupt. fig. 15 interrupt control diagram interrupt request bit interrupt enable bit interrupt disable flag brk instruction reset interrupt request
19 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 16 structure of registers related to interrupts b7 b0 edge polarity selection register (eg : address 00d4 16 ) interrupt control register 1 (icon1: address 00fe 16 ) b7 b0 interrupt control register 2 (icon2: address 00ff 16 ) interrupt request register 1 (ireq1: address 00fc 16 ) interrupt request register 2 (ireq2: address 00fd 16 ) b7 b0 b7 b0 b7 b0 timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit bus arbitration interrupt enable bit a-d conversion completion interrupt enable bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit serial i/o receive interrupt request bit serial i/o transmit interrupt request bit bus arbitration interrupt request bit a-d conversion completion interrupt request bit int 0 interrupt enable bit int 1 interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit 0 : interrupt disable 1 : interrupt enable int 0 interrupt request bit int 1 interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit 0 : no interrupt request 1 : interrupt request int 0 selection bit 0 : falling edge 1 : rising edge int 1 selection bit 0 : falling edge 1 : rising edge cntr 0 edge selection bit 0 : in event count mode, count rising edge. : in pulse output mode, start at h level output. : in pulse cycle measurement mode, measure a period from falling edge to falling edge. : in pulse width measurement mode, measure an h period. : in programmable one-shot output mode, generate one-shot h pulse after start at l output. : interrupt, falling edge active. 1 : in event count mode, count falling edge. : in pulse output mode, start at l level output. : in pulse cycle measurement mode, measure a period from rising edge to rising edge. : in pulse width measurement mode, measure an l period. : in programmable one-shot output mode, generate one-shot l pulse after start at h level output. : interrupt, rising edge active. cntr 1 edge selection bit 0 : in event count mode, count rising edge. : in pulse output mode, start at h level output. : in pulse cycle measurement mode, measure a period from falling edge to falling edge. : in pulse width measurement mode, measure an h period. : in programmable one-shot output mode, generate one-shot h pulse after start at l level output. : interrupt, falling edge active. 1 : in event count mode, count falling edge. : in pulse output mode, start at l output. : in pulse cycle measurement mode, measure a period from rising edge to rising edge. : in pulse width measurement mode, measure an l period. : in programmable one-shot output mode, generate one-shot l pulse after start at h output. : interrupt rising edge active. int 1 source selection bit at stp or wit 0 : p3 1 /int 1 1 : p0 0 C p0 7 l level (for key-on wake-up) not used (undefined at read) not used (undefined at read) 0 : interrupt disabled 1 : interrupt enabled 0 : no interrupt request 1 : interrupt requested not used (undefined at read) not used (undefined at read) 0 : interrupt disabled 1 : interrupt enabled 0 : no interrupt request 1 : interrupt requested
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 20 preliminar y notice: this is not a final specification. some parametric limits are subject to change. timers the 7480/7481 group has two 16-bit timers (timer x and timer y), and two 8-bit timers (timer 1 and timer 2). all the timers are of a count-down type. when the timer reaches ff 16 or 0000 16 , an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt re- quest bit corresponding to this timer is set to 1. at reading and setting the timer value to a 16-bit timer, be sure to read and set both high-order byte and low-order byte. at reading the count value from a 16-bit timer, read the high-order byte and the low-order byte in this order. at setting the count value in a 16-bit timer, set the low-order byte and the high-order byte in this order. the 16-bit timer cannot operate normally at reading during set op- eration or at setting during read operation. l timer x, timer y both timer x and timer y are 16-bit timers independent from each other. they can select 7 operating modes by setting the mode registers. the registers related to timer x and timer y are shown below. in the following, abbreviations will be used as register names. ? timer xy control register (txycon: address 00f8 16 ) ? port p4 direction register (p4d: address 00c9 16 ) ? timer x low-order (txl: address 00f0 16 ) ? timer x high-order (txh: address 00f1 16 ) ? timer y low-order (tyl: address 00f2 16 ) ? timer y high-order (tyh: address 00f3 16 ) ? timer x mode register (txm: address 00f6 16 ) ? timer y mode register (tym: address 00f7 16 ) ? edge polarity selection register (eg: address 00d4 16 ) ? interrupt request register 1 (ireq1: address 00fc 16 ) ? interrupt request register 2 (ireq2: address 00fd 16 ) ? interrupt control register 1 (icon1: address 00fe 16 ) ? interrupt control register 2 (icon2: address 00ff 16 ) for register structures, refer to each register structural diagram. in the following, each mode will be described. (1) timer mode/event count mode timer mode l mode selection this mode is selected by setting 000 in the timer x operating mode bits (b2b1b0) of txm and the timer y operating mode bits (b2b1b0) of tym. l count source selection the count source is f(x in )/2, f(x in )/8 or f(x in )/16. l interrupt when a timer underflows, the timer x interrupt request bit (b0) or timer y interrupt request bit (b1) of ireq1 is set to 1. l explanation of operation after reset release, the timer x stop control bit (b0) or timer y stop control bit (b1) of txycon is 1, and the timer stops. in the timer stop status, usually the timer value is set by writing the latch and timer at the same time. timer operation is started by setting 0 in b0 or b1 of txycon. when the timer reaches 0000 16 , an underflow occurs at the next count pulse, the corresponding timer latch is reloaded into the timer, and the count is continued. to change the timer value during count operation, the latch value is changed by writing to the latch only. at the next underflow reloading, the timer value is changed. event count mode l mode selection select the timer event count mode. this mode is selected by in- putting from the cntr 0 pin for timer x or from the cntr 1 pin for timer y (setting 11 in b7 and b6 of txm or 11 in b7 and b6 of tym). the count operation active edge is selected by setting in the cntr 0 edge selection bit (b2) or the cntr 1 edge selec- tion bit (b3) of eg. at 0, the rising edge is counted. at 1, the falling edge is counted. l interrupt the underflow interrupt is the same as the timer mode. l explanation of operation this operation is the same as that of the timer mode. in this mode, set the port in common with the cntr 0 /cntr 1 pin as an input port. figure 19 shows a timing diagram in the timer event count mode. (2) pulse output mode l mode selection this mode is selected by setting b2, b1 and b0 of txm or tym to 001. l count source selection the count source is f(x in )/2, f(x in )/8 or f(x in )/16.
21 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. the timer value provided before the start of measurement. figure 21 shows a timing diagram in the pulse cycle measurement mode. (4) pulse width measurement mode l mode selection this mode is selected by setting b2, b1 and b0 of txm or tym to 011. l count source selection the count source is f(x in )/2, f(x in )/8 or f(x in )/16. l interrupt the underflow interrupt is the same as the timer event count mode. set b2 or b3 of ireq2 to 1 as soon as pulse width measurement is completed. l explanation of operation while a timer operation stops select a timer count source. next, select a pulse width to be measured. a timer counts a period from a falling edge to a rising edge of the cntr 0 /cntr 1 pin input (l period) when b2 or b3 of eg is 1. a timer counts a period from a rising edge to a fall- ing edge of the cntr 0 /cntr 1 pin input (h period) when b2 or b3 of eg is set to 0. while a timer operation is enabled at setting b0 and b1 of txycon to 0, a timer starts to mea- sure a pulse width, and starts to count down from the count value provided before measurement. when the active edge is detected at measurement completion, 1s complement of the timer value is set in the timer latch. when the active edge is de- tected at measurement completion or measurement start, ffff 16 is set in the timer. when a timer underflows, a timer x or timer y interrupt occurs, and ffff 16 is set in the timer. a measurement value is held until the next measurement is completed. in this mode, set the port in common with the cntr 0 /cntr 1 pin as an input port. l interrupt the timer underflow interrupt is the same as the timer event count mode. l explanation of operation this operation is the same as the timer event count mode ex- cept that a timer outputs a pulse from the cntr 0 /cntr 1 pin in which the polarity of output level is inverted at each timer underflow. when the cntr 0 edge selection bit (b2) or cntr 1 edge selection bit (b3) of eg is 0, the output of the cntr 0 / cntr 1 pin is started with an h level output. when b2 or b3 of eg is 1, the output of this pin is started with an l level. in this mode, set the port in common with the cntr 0 /cntr 1 pin as an output port. n note while a timer operation stops the output level of the cntr 0 /cntr 1 pin is initialized to the value set in the cntr 0 edge selection bit or cntr 1 edge selection bit by writing to the timer. while a timer operation is enabled the output level of the cntr 0 /cntr 1 pin is inverted by changing the cntr 0 edge selection bit or cntr 1 edge selection bit. figure 20 shows a timing diagram in the pulse output mode. (3) pulse cycle measurement mode l mode selection this mode is selected by setting b2, b1 and b0 of txm or tym to 010. l count source selection the count source is f(x in )/2, f(xi n )/8 or f(x in )/16. l interrupt the underflow interrupt is the same as the timer event count mode. set b2 or b3 of ireq2 to 1 as soon as the pulse cycle measurement is completed. l explanation of operation while a timer operation stops select a timer count source. next, select a pulse cycle to be measured. when b2 or b3 of eg is 0, a timer counts a period from a falling edge to a falling edge of the cntr 0 /cntr 1 pin in- put. when b2 or b3 of eg is 1, a timer counts a period from a ris- ing edge to a rising edge of the cnrt 0 /cntr 1 pin input. while a timer operation is enabled at setting b0 and b1 of txycon to 0, a timer starts to mea- sure the pulse cycle, and starts to count down from the count value provided before measurement. when an active edge is detected at measurement completion or measurement start, 1's complement of the timer value is set to the timer latch and ffff 16 is set in the timer. when a timer underflows, a timer x or timer y interrupt occurs, and ffff 16 is set in the timer. a measurement value is held until the next measurement is completed. in this mode, set the port in common with the cntr 0 /cntr 1 pin as an input port. n note the timer value cannot be read in this mode. a timer value can be set while a timer operation stops (no measurement). since the timer latch of this mode becomes read only, do not per- form a write operation during measurement. the timer is set to ffff 16 only when the timer underflows or the active edge of pulse cycle measurement is detected. accordingly, the timer value at a start of measurement depends on
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 22 preliminar y notice: this is not a final specification. some parametric limits are subject to change. n note the timer value cannot be read in this mode. a timer value can be set while a timer operation stops (not under pulse width measure- ment). since the timer latch of this mode becomes read only, do not per- form a write operation during measurement. the timer is set to ffff 16 only when a timer underflows or when the active edge of pulse width measurement is detected. accordingly, the timer value at a start of measurement depends on the timer value provided before the start of measurement. figure 22 shows a timing diagram in the pulse width measurement mode. (5) programmable waveform generation mode l mode selection this mode is selected by setting b2, b1 and b0 of txm or tym to 100. l count source selection the count source is f(x in )/2, f(x in )/8 or f(x in )/16. l interrupt the underflow interrupt is the same as the timer event count mode. the int 0 interrupt request bit (b0) or int 1 interrupt re- quest bit (b1) of ireq2 is set to 1 by detecting an active edge of the int pin. l explanation of operation this operation is the same as that of the timer event count mode, except that a timer outputs the level of the value set in the output level latch (b4) of txm or tym from the cntr 0 / cntr 1 pin each time the timer underflows. after the timer underflows, if the values of the output level latch and timer latch are changed, the timer can output an optional waveform from the cntr 0 /cntr 1 pin. in this mode, set the port in common with the cntr 0 /cntr 1 pin as an output port. in this mode, if the trigger selection bit of txm or tym is set to 1 and the count stop control bit of txycon is set to 0 (count operation), a timer can be started concurrently with the occur- rence of a trigger (input signal of int 0 /int 1 pin). a timer starting trigger is set in the int 0 edge selection bit (b0) or int 1 edge selection bit (b1) of eg. at 0, the falling edge is active. at 1, the rising edge is active. when the count stop control bit is 1 (count status), a timer is not started at the oc- currence of a trigger. figure 23 shows a timing diagram in the programmable wave- form generation mode. (6) programmable one-shot output mode l mode selection this mode is selected by setting b2, b1 and b0 of txm or tym to 101. l count source selection the count source is f(x in )/2, f(x in )/8 or f(x in )/16. l interrupt the underflow interrupt is the same as the timer event count mode. one-shot output trigger is set in the int 0 edge selection bit (b0) or int 1 edge selection bit (b1) of eg. at 0, the falling edge is active. at 1, the rising edge is active. the int 0 inter- rupt request bit (b0) or int 1 interrupt request bit (b1) of ireq2 is set to 1 by detecting an active edge of the int pin. l explanation of operation in case of one-shot output h (b2, b3 of eg = 0) while a timer operation stops the output level of the cntr 0 /cntr 1 pin is initialized to l at mode selection. set the one-shot width in txh, txl, tyh and tyl. while a timer operation stops, a trigger (input signal of int 0 /int 1 pin) cannot occur. while a timer operation is enabled at detecting a trigger, a timer outputs h from the cntr 0 / cntr 1 pin, and outputs l at a timer underflow. in case of one-shot output l (b2, b3 of eg = 1) while a timer operation stops the output level of the cntr 0 /cntr 1 pin is initialized to h at mode selection. set the one-shot width in txh, txl, tyh and tyl. while a timer operation stops, a trigger (input signal of the int 0 /int 1 pin) cannot occur. while a timer operation is enabled at the detection of a trigger, a timer outputs l from the cntr 0 / cntr 1 pin and outputs h at a timer underflow. in this mode, set the port in common with the cntr 0 /cntr 1 pin as an output port. n note l input a trigger width over 250 ns to the int 0 /int 1 pin. l if the value of the cntr 0 edge selection bit or cntr 1 edge se- lection bit is changed while one-shot output is enabled or one-shot output occurs, the output level from the cntr 0 / cntr 1 pin changes. figure 24 shows a timing diagram in the programmable one- shot output mode.
23 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. same time. at writing only to the timer latch, when the write timing for the timer latch is almost equal to the underflow timing, the value that is set in the timer may not be constant. l read control for timer x/timer y when the pulse cycle measurement mode or pulse width mea- surement mode is selected, the timer value cannot be read out. in the other modes, the timer value can be read regardless of count operation and count stop. however, the timer latch value cannot be read out. l note on cntr 0 , cntr 1 , int 0 , int 1 interrupt polarity selection when the cntr 0 /cntr 1 edge selection bit or int 0 /int 1 inter- rupt edge selection bit is set, this affects the respective interrupt polarity. n (n + m) (7) pwm mode l mode selection this mode is selected by setting b2, b1 and b0 of txm or tym to 110. l count source selection the count source is f(x in )/2, f(x in )/8 or f(x in )/16. l interrupt at the rising edge of the cntr 0 /cntr 1 output, set the timer x interrupt request bit (b0) or timer y interrupt request bit (b1) of ireq1 to 1. l explanation of operation in the case of timer x, the pwm waveform is output from the cntr 0 pin. in the case of timer y, the pwm waveform is output from the cntr 1 pin. the pwm waveform h period is determined by the setting value n (n=0 to 255) of txh or tyh. the l period is deter- mined by the setting value m (m=0 to 255) of txl or tyl. the pwm cycle is as follows: pwm cycle = (n + m) 5 ts pwm output duty = ts: timer x/timer y count source cycle while a timer operation stops the timer value is set in txl, txh, tyl and tyh by writing to the timer and timer latch at the same time. the output of the cntr 0 /cntr 1 pin is initialized to h by setting this timer value. while a timer operation is enabled when b1 and b0 of txycon are set to 0, h is output during the period of the setting value of txh or tyh. after that, l is output during the period of the setting value of txl or tyl. then, these operations will be repeated. the pwm output sub- sequent to an underflow can be changed by setting the timer value in txl, txh, tyl, tyh by writing only to the timer latch. in this mode, set the port in common with the cntr 0 /cntr 1 pin as an output port. n note l when the pwm h period is set to 00 16 , the pwm output is always l level. l when the pwm l period is set to 00 16 , the pwm output is al- ways h level. l when the pwm h period is set to 00 16 and the l period is set to 00 16 , the pwm output is always l level. l when at least one of the pwm h period and l period is set to 00 16 , a timer x interrupt request/timer y interrupt request does not occur. l when the timer latch is set at 00 16 , the timer counts down, so its value is not constant. figure 25 shows a timing diagram in the pwm mode. n note on all modes l write control for timer x, timer y timer x and timer y can select either writing to both timer latch and timer or writing only to the timer latch by b3 of txm or tym. at writing only to the timer latch, a value is set in the timer latch by writing the value in the timer x/timer y address, so the timer is updated at the next underflow. after reset release, writing to both the timer latch and timer is selected. at this status, when a value is written in the timer x/timer y ad- dress, the value is set in both the timer and timer latch at the
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 24 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 17 block diagram of timer x and timer y pwm generating circuit d t q programmable one-shot output circuit t q q s programmable waveform generation mode pulse output mode cntr 0 edge selection bit 1 0 programmable one-shot output mode pwm mode cntr 0 edge selection bit timer x (low-order) latch timer x (high-order) latch timer x (high-order)timer x (low-order) edge detecting circuit timer x stop control bit timer x count source selection bit pulse width measurement mode pulse cycle measurement mode cntr 0 edge selection bit 001 100 101 110 timer x operating mode bits programmable one-shot output mode pwm mode output level latch p3 0 /int 0 p4 0 /cntr 0 p4 0 direction register p4 0 latch f(x in )/2 f(x in )/8 f(x in )/16 1 0 1 0 int 0 interrupt request timer x interrupt request pulse output mode d t q programmable one-shot output circuit t q q s programmable waveform generation mode pulse output mode cntr 1 edge selection bit 1 0 programmable one-shot output mode pwm mode cntr 1 edge selection bit edge detecting circuit timer y count source selection bit 001 100 101 110 timer y operating mode bits programmable one-shot output mode pwm mode output level latch p3 1 /int 1 p4 1 /cntr 1 p4 1 direction register p4 1 latch f(x in )/2 f(x in )/8 f(x in )/16 1 0 pulse output mode data bus 1 0 programmable waveform generation mode timer x trigger selection bit timer y stop control bit d t q 1 0 programmable waveform generation mode timer y trigger selection bit cntr 1 edge selection bit 1 0 1 0 int 0 edge selection bit 1 0 int 1 edge selection bit pulse width measurement mode pulse cycle measurement mode pwm generating circuit timer y (low-order) latch timer y (high-order) latch timer y (high-order)timer y (low-order) cntr 0 interrupt request int 1 interrupt request timer y interrupt request cntr 1 interrupt request d t q
25 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 18 structure of timer x/timer y mode register and timer xy control register timer y mode register (tym : address 00f7 16 ) b7 b0 timer x mode register (txm : address 00f6 16 ) timer xy control register (txycon : address 00f8 16 ) not used (all 0 at read) b7 b0 b7 b0 timer x stop control bit 0 : count operation 1 : count stop timer y stop control bit 0 : count operation 1 : count stop timer x operating mode bits b2 b1 b0 0 0 0 : timer event count mode 0 0 1 : pulse output mode 0 1 0 : pulse cycle measurement mode 0 1 1 : pulse width measurement mode 1 0 0 : programmable waveform generation mode 1 0 1 : programmable one-shot output mode 1 1 0 : pwm mode 1 1 1 : not used timer x write control bit 0 : writing to both latch and timer 1 : writing to latch only output level latch 0 : l output 1 : h output timer x trigger selection bit 0 : timer x free run in programmable waveform generation mode 1 : trigger occurrence (input signal of int 0 pin) and timer x start in programmable waveform generation mode. timer x count source selection bits b7 b6 00 : f(x in )/2 0 1 : f(x in )/8 1 0 : f(x in )/16 1 1 : input from cntr 0 pin timer y operating mode bits b2 b1 b0 0 0 0 : timer event count mode 0 0 1 : pulse output mode 0 1 0 : pulse cycle measurement mode 0 1 1 : pulse width measurement mode 1 0 0 : programmable waveform generation mode 1 0 1 : programmable one-shot output mode 1 1 0 : pwm mode 1 1 1 : not used timer y write control bit 0 : writing to both latch and timer 1 : writing to latch only output level latch 0 : l output 1 : h output timer y trigger selection bit 0 : timer y free run in programmable waveform generation mode 1 : trigger occurrence (input signal of int 1 pin) and timer y start in programmable waveform generation mode. timer y count source selection bits b7 b6 0 0 : f(x in )/2 0 1 : f(x in )/8 1 0 : f(x in )/16 1 1 : input from cntr 1 pin
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 26 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 19 timing diagram in timer mode/event count mode fig. 20 timing diagram in pulse output mode tr tr tr ffff 16 tl 0000 16 tl : value set in timer latch tr : timer interrupt request tr tr tr ffff 16 tl 0000 16 tl : value set in timer latch tr : timer interrupt request cntr : cntr 0 /cntr 1 interrupt request tr output waveform from cntr 0 /cntr 1 pin cntr cntr (cntr polarity selection bit ??: falling edge active)
27 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 21 timing diagram in pulse cycle measurement mode (at rising edge interval measurement) fig. 22 timing diagram in pulse width measurement mode (at l section measurement) tr ffff 16 0000 16 tr : timer interrupt request cntr: cntr 0 /cntr 1 interrupt request tr input signal from cntr 0 /cntr 1 pin cntr cntr cntr cntr ffff 16 +t1 t2 t3 ffff 16 cntr 0 /cntr 1 interrupt polarity is active at rising edge. t3 t2 t1 tr ffff 16 0000 16 tr : timer interrupt request cntr : cntr 0 /cntr 1 interrupt request input signal from cntr 0 /cntr 1 pin cntr cntr cntr ffff 16 +t2 t1t3 cntr 0 /cntr 1 interrupt polarity is active at rising edge, and pulse l width is measured. t3 t2 t1
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 28 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 23 timing diagram in programmable waveform generation mode (when trigger selection bit = 1) fig. 24 timing diagram in programmable one-shot output mode tr ffff 16 0000 16 l : initial value of tl h , tl l tr : timer interrupt request cntr : cntr 0 /cntr 1 interrupt request output waveform from cntr 0 /cntr 1 pin t3 t3 t2 t1 l tr tr tr l t1 t2 input signal from int 0 /int 1 pin (cntr polarity selection bit ??: falling edge active) cntr cntr ffff 16 0000 16 l : one-shot pulse width tr : timer interrupt request cntr : cntr 0 /cntr 1 interrupt request output waveform from cntr 0 / cntr 1 pin l tr tr tr l l l input signal from int 0 /int 1 pin (cntr polarity selection bit ??: falling edge active) cntr cntr cntr
29 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 25 timing diagram in pwm mode timer x/timer y count source timer x/timer y pwm output ts n 5 t sm 5 t s (n+m) 5 t s tr cntr cntr : cntr 0 /cntr 1 interrupt request (cntr polarity selection bit 0 : falling edge active) tr tr : timer interrupt note : a pwm waveform with duty n/(n+m) and cycle (n+m) 5 ts is output. ? txh/tyh setting value: n= 0 C 255 ? txl/tyl setting value: m = 0 C 255 ? timer x/timer y count source cycle: ts ? n+m = 0 C 510
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 30 preliminar y notice: this is not a final specification. some parametric limits are subject to change. (1) timer mode the frequency of f(x in )/8, f(x in )/64, f(x in )/128 or f(x in )/256 is counted. (2) programmable waveform generation mode this operation is the same as the timer mode, except that a timer outputs the level of the value set in the output level latch of the timer 1 mode register/timer 2 mode register from the t 0 or t 1 pin each time a timer underflows. after the timer underflows, the timer can output an optional wave- form from the t 0 or t 1 pin if the values of the output level latch and timer latch are changed. in this mode, set the port in common with the t 0 /t 1 pin as an out- put port. fig. 26 block diagram of timer 1, timer 2 l timers 1 and 2 timer 1 and timer 2 are the 8-bit timers. they can select the fol- lowing 2 modes by setting timer 1 mode register and timer 2 mode register. ? timer mode ? programmable waveform generation mode when the count source is changed, set it again as the timer value may go wrong. fig. 27 structure of timer 1/timer 2 mode register timer stop control bit 0 : count operation 1 : count stop timer 1 mode register (t1m : address 00f9 16 ) timer 2 mode register (t2m : address 00fa 16 ) b7 b0 timer operation mode bit 0 : timer mode 1 : programmable waveform generation mode output level latch 0 : l output 1 : h output timer count source selection bits b7 b6 0 0 : f(x in )/8 0 1 : f(x in )/64 1 0 : f(x in )/128 1 1 : f(x in )/256 not used (0 at read) not used (0 at read) timer mode register count stop control bit f(x in )/8 timer interrupt request bit 8 8 t tl 8 8 data bus data bus f(x in )/64 f(x in )/128 f(x in )/256 output level latch t d q timer count source selection bits 00 01 10 11 t 0 , t 1 output
31 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. the serial i/o mode selection bit of the serial i/o control register (address 00e2 16 ) to 1. in the clock synchronous serial i/o, the transmitter-side microcom- puter and the receiver-side microcomputer must use the same clock for serial i/o operation. if an internal clock is used as oper- ating clock, a transfer is started by a write signal to the transmit/ receive buffer register. fig. 28 block diagram of clock synchronous serial i/o fig. 29 operation of clock synchronous serial i/o function data bus data bus receive buffer register clock control circuit serial i/o control register falling edge detection serial i/o status register f/f 1/4 1/4 1/4 transmit shift register shift completion flag (tsc) transmit interrupt request (ti) transmit buffer empty flag (tbe) receive buffer full flag (rbf) receive interrupt request (ri) serial i/o synchronous clock selection bit (scs) frequency division ratio 1/(n+1) p1 6 p1 4 shift clock p1 5 p1 7 clock control circuit receive shift register transmit shift register transmit buffer register t x d s rdy s clk r x d x in s rdy output enable bit (srdy) address 00e0 16 address 00e2 16 address 00e0 16 address 00e1 16 address 00e4 16 brg count source selection bit (css) transmit interrupt source selection bit (tic) transmit enable bit (te) receive enable bit (re) serial i/o enable bit (sioe) baud rate generator serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation when serial i/o is in opera- tion. (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode can be selected by setting d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tbe = 0 tbe = 1 tsc = 0 rbf = 1 tsc = 1 overrun error (oe) detection transmit/receive shift clock, 1/8 C 1/8192 of internal clock, or external clock serial output txd serial input rxd receive enable signal s rdy write signal to receive/ transmit buffer register (address 00e0 16 ) notes 1 : the transmit interrupt (ti) can be selected to be generated either when the transmit buffer is empty (tbe = 1) or after the transmit shift operation is completed (tsc = 1) by using the transmit interrupt source selection bit (tic) of the serial i/o control register. 2 : if data is written to the transmit buffer register when tsc = 0, the transmit clock is generated continuously, and serial data is output continuously from the txd pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 32 preliminar y notice: this is not a final specification. some parametric limits are subject to change. each of the transmit and receive registers has a buffer register (the same address on memory). since the shift register cannot be written to or read from directly, transmit data is written to the trans- mit buffer register and receive data is read from the receive buffer register. these buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession. (2) asynchronous serial i/o (uart) mode the uart mode can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to 0. eight serial data transfer formats can be selected, and the transfer formats to be used by a transmitter and a receiver must be identi- cal. fig. 30 block diagram of uart serial i/o fig. 31 operation of uart serial i/o function receive buffer register clock control circuit serial i/o control register baud rate generator serial i/o status register 1/4 1/4 transmit shift register shift completion flag (tsc) transmit interrupt request (ti) transmit buffer empty flag (tbe) receive buffer full flag (rbf) receive interrupt request (ri) frequency division ratio 1/(n+1) p1 4 p1 5 p1 6 receive shift register transmit shift register transmit buffer register t x d s clk r x d x in address 00e0 16 address 00e2 16 address 00e0 16 address 00e1 16 address 00e4 16 7-bit 1/16 1/16 uart control register st/sp/pa generation serial i/o synchronous clock selection bit (scs) oe sp detection 8-bit pe fe st detection address 00e3 16 receive enable bit (re) transmit enable bit (te) character length selection bit (chas) character length selection bit (chas) brg count source selection bit (css) data bus data bus serial i/o enable bit (sioe) serial i/o synchronous clock selection bit (scs) transmit interrupt source selection bit (tic) st d 0 d 1 sp st d 0 d 1 sp transmit or receive clock transmit buffer register write signal serial output txd receive buffer register read signal serial input rxd tbe=0 tsc=0 tbe=0 tbe=1 rbf=0 rbf=1 rbf=1 tsc=1 1 start bit 7/8 data bit 1/0 parity bit 1/2 stop bit st d 0 d 1 sp st d 1 sp * ] generated at 2nd bit in 2 stop bit mode notes 1 : error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit during reception). 2 : the transmit interrupt (ti) can be selected to be generated when either tbe=1 or tsc=1, depending on the setting of the transmit interrupt source selection bit of the serial i/o control register. 3 : the receive interrupt (ri) is set when the rbf flag becomes 1. d 0 tbe=1
33 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. b7 b0 uart control register uartcon (address 00e3 16 ) character length selection bit (chas) 0 : 8-bit 1 : 7-bit not used (1 at read) parity enable bit (pare) 0 : parity disabled 1 : parity enabled parity selection bit (pars) 0 : even parity 1 : odd parity stop bit length selection bit (stps) 0 : 1 stop bit 1 : 2 stop bits b7 b0 serial i/o control register siocon (address 00e2 16 ) brg count source selection bit (css) 0 : f(x in )/4 1 : f(x in )/16 serial i/o synchronous clock selection bit (scs) 0 : brg output/4 (when clock synchronous serial i/o is selected) brg output/16 (when uart is selected) 1 : external clock input (when clock synchronous serial i/o is selected) external clock input/16 (when uart is selected ) s rdy output enable bit (srdy) 0 : p1 7 pin operates as ordinary i/o pin. 1 : p1 7 pin operates as s rdy output pin. transmit interrupt source selection bit (tic) 0 : interrupt when transmit buffer is empty. 1 : interrupt when transmit shift operation is completed. transmit enable bit (te) 0 : transmit disabled 1 : transmit enabled receive enable bit (re) 0 : receive disabled 1 : receive enabled serial i/o mode selection bit (siom) 0 : asynchronous serial i/o (uart) 1 : clock synchronous serial i/o serial i/o enable bit (sioe) 0 : serial i/o disabled (p1 4 to p1 7 : ordinary i/o ports) 1 : serial i/o enabled (p1 4 to p1 7 : serial i/o function pins) b7 b0 transmit buffer empty flag (tbe) 0 : buffer full 1 : buffer empty receive buffer full flag (rbf) 0 : buffer empty 1 : buffer full transmit shift register shift completion flag (tsc) 0 : transmit shift in progress 1 : transmit shift completed overrun error flag (oe) 0 : no error 1 : overrun error parity error flag (pe) 0 : no error 1 : parity error framing error flag (fe) 0 : no error 1 : framing error summing error flag (se) 0 : (oe)u(pe)u(fe)=0 1 : (oe)u(pe)u(fe)=1 not used (1 at read) serial i/o status register siosts (address 00e1 16 ) [serial i/o control register] siocon the serial i/o control register consists of 8 control bits for control of the serial i/o. [uart control register] uartcon the uart control register is a 4-bit control register which is valid when uart is selected. this 4-bit control register sets a data for- mat for serial data transfer. [serial i/o status register] siosts this is a 7-bit read-only register consisting of flags that indicate the serial i/o operating status and different error flags. the 3 bits of bit 4 to bit 6 are valid only in the uart mode. the receive buffer full flag is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. writing to the serial i/o status register clears all the error flags (oe, pe, fe, se). all the bits of this register are initialized to 0 at reset. however, if the transmit enable bit of the serial i/o control register is set to 1, bit 2 and bit 0 become 1. [transmit buffer register/receive buffer register] tb/rg the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is a write-only type and the receive buffer register is a read-only type. if a character bit length is 7 bits, the msb of the receive data stored in the receive buffer is 0. [baud rate generator] brg the baud rate generator determines a baud rate for serial transfer. the baud rate generator, being an 8-bit counter with a reload reg- ister, divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. fig. 32 structure of serial i/o related registers (siosts, uartcon, siocon)
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 34 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 7480/7481 group serial i/o interface driver/ receiver txd rxd lan data bus bus arbitration interrupt the 7480/7481 group is provided with a built-in bus arbitration in- terrupt as a function for bus conflict system communication. at such bus conflict system communication, as shown in figure 33, if transmit data cannot be transmitted to the lan data bus due to a transmit data collision, the data collision can be detected by the bus arbitration interrupt. fig. 33 example of bus conflict system communication
35 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. a transmit data collision is detected between lsb and msb of transmit data in the clock synchronous serial i/o mode or between the start bit and stop bit of transmit data in the uart mode. bus collision detection can be performed by both the internal clock and the external clock. a block diagram is shown in figure 34. a timing diagram is shown in figure 35. a bus collision detection control register is shown in figure 36. fig. 34 block diagram of bus arbitration interrupt circuit fig. 36 structure of bus collision detection control register t x d r x d shift clock d q bus arbitration interrupt request bus collision detection enable bit te transmit shift clock transmit pin txd receive pin rxd bus arbitration interrup t generation data collision bus collision detection the 7480/7481 group can detect a bus collision by setting the bus collision detection enable bit to 1. when transmission is started in the clock synchronous or asyn- chronous (uart) serial i/o mode, the transmit pin txd is compared with the receive pin rxd in synchronization with a rising edge of transmit shift clock. if they do not coincide with each other, a bus arbitration interrupt request occurs (bus collision detection). fig. 35 timing diagram of bus arbitration interrupt b7 b0 bus collision detection control register (busarbcon address 00e5 16 ) bus collision detection enable bit 0 : collision detection disabled 1 : collision detection enabled not used (0 at read)
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 36 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 37 priority control at simplified saej1850 bus+ bus- unit a unit b unit a lan data bus unit b continue to transmit stop transmitting data collision lan data bus application example priority control at simplified saej1850 at simplified saej1850 communication, when multiple units start to transmit data at the same time, priority control is exerted. on the lan data bus, the h level has priority over the l level. when an h level collides with an l level, the lan data bus sta- tus goes to the h level. for example, when unit a outputs h and unit b outputs l at the same time in figure 37, the lan data bus goes to h. accord- ingly, unit a takes priority of control and continues its transmission, and unit b stops its transmission immediately. in this way, the 7480/7481 group exerts priority control for each bit and finally allows only the highest-priority unit to transmit data.
37 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d converter for a-d conversion, the 8-bit successive comparison method is used. figure 38 shows a block diagram of a-d conversion. con- version is automatically performed once started by the program. there are 8 analog input pins that are in common with p2 7 to p2 0 of port p2 (4 pins of p2 3 to p2 0 in the 7480 group). pin inputs to be a-d converted are selected by bit 2 to bit 0 of the a-d control register (address 00d9 16 ). bit 3 of the a-d control reg- ister is an a-d conversion completion bit. this bit is 0 during a-d conversion and 1 after completion of it. accordingly, it is possible by checking this bit to know whether a-d conversion is completed or not. figure 39 shows the relationship between the contents of the a-d control register and input pins to be selected. the a-d conversion register (address 00da 16 ) stores conversion results, so it is possible to know them by reading the contents of this register. next, the procedure for executing a-d conversion will be ex- plained below. first, set values in bit 2 to bit 0 of the a-d control register and select pins to be a-d converted. next, clear the a-d conversion completion bit to 0. with this write operation, a-d conversion is started. the a-d conversion is com- pleted after the lapse of 50 machine cycles (12.5 s at f(x in )= 8 mhz), and the a-d conversion completion bit is set to 1. the a-d conversion interrupt request bit is also set to 1. conversion re- sults are stored in the a-d conversion register. fig. 38 block diagram of a-d converter circuit comparator a-d control circuit a-d conversion register (address 00da 16 ) switch tree ladder resistor a-d conversion completion interrupt request v ss (note 1) v ref 1 : av ss for the 44p6n package of the 7481 group. 2 : the 7480 group is not provided with p2 4 /in 4 to p2 7 /in 7 . p2 0 /in 0 p2 1 /in 1 p2 2 /in 2 p2 3 /in 3 p2 4 /in 4 p2 5 /in 5 p2 6 /in 6 p2 7 /in 7 data bus a-d control register (address 00d9 16 ) b4 b0 channel selector notes
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 38 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 39 structure of a-d control register a-d control register adcon (address 00d9 16 ) analog input pin selection bit s 000 : p2 0 /in 0 001 : p2 1 /in 1 010 : p2 2 /in 2 011 : p2 3 /in 3 100 : p2 4 /in 4 101 : p2 5 /in 5 110 : p2 6 /in 6 111 : p2 7 /in 7 a-d conversion completion bit 0 : conversion in progress 1 : conversion completed v ref connection selection bit 0: disconnect between v ref pin and ladder resistor 1: connect between v ref pin and ladder resistor b7 b0 note : do not perform setting in the 7480 group. (note) not used (undefined at read)
39 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. watchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of a 7-bit watchdog timer l and an 8- bit watchdog timer h. l initial value of watchdog timer by a reset or writing to the watchdog timer h, the watchdog timer h is set to ff 16 and the watchdog timer l is set to 7f 16 . any in- struction that permits generating a write signal can be used; for example, sta, ldm, clb, etc. write data has no significance, so the above values are set regardless of that data. l operation of watchdog timer the watchdog timer stops at reset, and writing a value in the watchdog timer h causes it to start to count down. when bit 7 of the watchdog timer h becomes 0, an internal reset occurs. the reset status is released as soon as the release reset time is up. after that, the 7480/7481 group runs the program from the re- set vector address. it is programmed that the watchdog timer h can be set before bit 7 of the watchdog timer h is cleared to 0. if the watchdog timer h is never written, the watchdog timer does not function. when the stp instruction is executed, the clock stops and the watchdog timer also stops. the count is restarted as soon as the stop mode is released. (note) on the other hand, the watchdog timer does not stop after execution of the wit instruc- tion. the timing from writing to the watchdog timer h to clearing bit 7 of the watchdog timer h to 0 is shown below. (f(x in )=8 mhz) ? when bit 3 of the cpu mode register is 0 ............. 16.384 ms ? when bit 3 of the cpu mode register is 1 ............ 32.768 ms note: since the watchdog timer still counts for the stop release waiting time (about 2048 cycles of x in ), bit 7 of the watch- dog timer h should not be cleared to 0 in this period. fig. 40 block diagram of watchdog timer watchdog timer l (7) watchdog timer h (8) 1/8 1/16 0 1 watchdog timer l count source selection bit write 7f 16 to the watchdog timer register write ff 16 to the watchdog timer register data bus reset circuit internal reset reset f(x in ) bit7
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 40 preliminar y notice: this is not a final specification. some parametric limits are subject to change. stp/wit instruction control the stp instruction and the wit instruction can be enabled or disabled selectively by using the stp instruction operation control register. to cope with a program runaway after reset, the stp in- struction and the wit instruction are disabled in the initial status. the stp and wit instructions can be set as enable/disable only by writing to the stp instruction operation control register twice successively so as not to stop the oscillation clock even if a write data error is caused by program runaway. figure 41 shows a structure of the stp instruction operation control register. fig. 41 structure of stp instruction operation control register explanation of stp instruction operation control register the stp instruction operation control register will be enabled by writing data to the same address twice successively. if data is not written in continuous form, the written data is not valid but the pre- vious value is held. if an interrupt is received while the same data is written twice, there is a possibility that the write instruction in the interrupt rou- tine may be executed. for this reason, rewriting is required after interrupt disable. figure 42 shows a reference example of data re- writing. fig. 42 reference example of data rewriting b7 b0 stp instruction operation control register (stpcon: address 00de 16 ) stp instruction and wit instruction enable/disable selection bit (note) 0 : stp/wit instruction enabled 1 : stp/wit instruction disabled not used (0 at read) the stp instruction and the wit instruction are disabled in the initial status. when using these instructions, set bit 0 of the stp instruction operation control register to 1, then set this bit to 0. (writing twice successively) when not using the stp and wit instructions, set this bit to 1 either once or twice. note : l stp/wit instruction enable sei ldm #01h, 0deh ldm #00h, 0deh cli use only in interrupt enable status interrupt disable in this period l stp/wit instruction disable sei ldm #01h, 0deh ldm #01h, 0deh cli use only in interrupt enable status interrupt disable in this period
41 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. recovery from power-down status by key input interrupt (key-on wake-up) key-on wake-up is one way of recovery from a power-down sta- tus by using the stp or wit instruction. if an l level voltage is input to any pin of port p0 when bit 5 of the edge polarity selection register is 1, an interrupt occurs, and a recovery can be made to the normal operating state. if a key matrix of active l with port p0 as an input port is constructed, a recovery can be made to the normal operating status by pressing a key. the key input interrupt is in common with the int 1 interrupt. when bit 5 of the edge polarity selection register is set to 1, the key in- put interrupt function is selected. if this bit is set to 1 except in the power-down status, both int 1 and key-on wake-up are invali- dated. fig. 43 block diagram of interrupt input/key-on wake-up circuit p4 1 /cntr 1 p4 0 /cntr 0 p3 0 /int 0 p3 1 /int 1 p0 7 p0 1 eg 3 port p4 1 data read circuit cntr 1 interrupt request signal port p4 0 data read circuit eg 0 port p3 0 data read circuit int 0 interrupt request signal port p3 1 data read circuit int 1 interrupt request signal cpu stop status signal port p0 data read circuit eg 1 eg 5 p0 0 eg 2 cntr 0 interrupt request signal pull-up control register direction register pull-up control register direction register pull-up control register direction register
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 42 preliminar y notice: this is not a final specification. some parametric limits are subject to change. clock generating circuit the 7480/7481 group is provided with a built-in oscillation circuit. an oscillation circuit can be formed by connecting a resonator be- tween x in and x out . use the manufacturer's recommended values for constants such as capacitance, which will differ de- pending on each resonator. the 7480/7481 group has a built-in feedback resistor between the x in and x out pins, so an external resistor can be omitted. l frequency control (1) high-speed mode the frequency applied to the clock input pin x in divided by 2 is used as the internal clock f . this mode is set after reset release. (2) medium-speed mode the frequency applied to the clock input pin x in divided by 8 is used as the internal clock f . l oscillation frequency (1) stop mode if the stp instruction is executed, the internal clock f stops at an h level, and the oscillator stops. at this time, timer 1 is set to ff 16 , and f(x in )/8 is forcibly connected to the count source of timer 1. accordingly, set the timer 1 interrupt enable bit to the dis- able status (0) before execution of the stp instruction. when a reset or an external interrupt is accepted, oscillation is re- started, but the internal clock f is supplied to the cpu after timer 1 underflows. this is because when an external resonator is used, some time is required until a start of oscillation. (2) wait mode if the wit instruction is executed, the internal clock f stops at an h level. but, the oscillator does not stop. when a reset or inter- rupt is accepted, the stop status is released. the microcomputer can execute any instruction immediately, because the oscillator does not stop. fig. 44 external circuit of ceramic resonator fig. 45 external clock input circuit x in x out c out c in r d x in x out external oscillation circuit open v cc v ss duty ratio 50%
43 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 46 block diagram of clock generating circuit q r s q r s q r s q r s q r s x in x out 1/2 1/4 1/4 timer 1 reset stp instruction reset interrupt disable flag interrupt request stp instruction wit instruction internal clock 1 0 cm 6
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 44 preliminar y notice: this is not a final specification. some parametric limits are subject to change. reset circuit the microcomputer is put into a reset status by holding the _____ reset pin at the l level for 2 s or more when the power source voltage is 2.7 to 5.5 v and x in is in stable oscillation. _____ after that, this reset status is released by returning the reset pin to the h level. the program starts from the address having the contents of address ffff 16 as high-order address and the con- tents of address fffe 16 as low-order address. note that the reset input voltage should be 0.32 v or less when the power source voltage passes 2.7 v. fig. 47 reset circuit diagram fig. 48 reset sequence reset v cc reset v cc power source voltage 0v reset input voltage 0v 0.12v cc power on (note) note : reset release voltage v cc = 2.7 v power source voltage detecting circuit ? ??? fffe 16 ffff 16 ad h,l ????ad l ad h x in f reset internal reset address data sync x in 2048 clock cycle reset address from the vector table notes 1 : the frequency relation between f(x in ) and is f(x in )=2f( ). 2 : the mark ? means that the address is changeable depending on the previous state. ff
45 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 49 internal state of microcomputer at reset : at reset release, the read value is undefined. 0000 contents of address ffff 16 address 1 ( 1 ) port p0 direction register (p0d) (c1 16 ) ? ? ? contents of address fffe 16 ( 2 ) port p1 direction register (p1d) (c3 16 ) ? ? ? ( 4 ) port p5 direction register (p5d) (cb 16 ) ? ? ? ( 5 ) port p0 pull-up control register (p0pcon) (d0 16 ) ? ? ? ( 6 ) port p1 pull-up control register (p1pcon) (d1 16 ) ? ? ? ( 8 ) edge polarity selection register (eg) (d4 16 ) ? ? ? ( 9 ) a-d control register (adcon) (d9 16 ) ? ? ? (22) timer y mode register (tym) (f7 16 ) ? ? ? (23) timer xy control register (txycon) (f8 16 ) ? ? ? (24) timer 1 mode register (t1m) (f9 16 ) ? ? ? (25) timer 2 mode register (t2m) (fa 16 ) ? ? ? (26) cpu mode register (cpum) (fb 16 ) ? ? ? (27) interrupt request register 1 (ireq1) (fc 16 ) ? ? ? (28) interrupt request register 2 (ireq2) (fd 16 ) ? ? ? (29) interrupt control register 1 (icon1) (fe 16 ) ? ? ? (30) interrupt control register 2 (icon2) (ff 16 ) ? ? ? (31) program counter (pc h ) (32) processor status register (ps) ( 3 ) 16 ) ? ? ? (10) stp instruction operation control register (stpcon) (de 16 ) ? ? ? (11) serial i/o status register (siosts) (e1 16 ) ? ? ? (12) serial i/o control register (siocon) (e2 16 ) ? ? ? (13) uart control register (uartcon) (e3 16 ) ? ? ? (15) watchdog timer h (wdth) (ef 16 ) ? ? ? (21) timer x mode register (txm) (f6 16 ) ? ? ? (pc l ) 0000 00 10 0000 1 1 11 ( 7 ) port p4p5 input control register (p4p5con) (d2 16 ) ? ? ? (14) bus collision detection control register (busarbcon) (e5 16 ) ? ? ? 0000 ff 16 1 0 0 00000 11 000000 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 (20) timer 1 (t1) (f4 16 ) ? ? ? (19) timer y high-order (tyh) (f3 16 ) ? ? ? ff 16 ff 16 (18) timer y low-order (tyl) (f2 16 ) ? ? ? (17) timer x high-order (txh) (f1 16 ) ? ? ? ff 16 ff 16 (16) timer x low-order (txl) (f0 16 ) ? ? ? ff 16 00 16 0000 0 1000 0 note : some kinds of microcomputers do not use some of these bits. refer to the structure of each register. 00 000 0000 0000 b7 b0 port p4 direction register (p4d) (c9
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 46 preliminar y notice: this is not a final specification. some parametric limits are subject to change. built-in programmable rom versions m37480e8-xxxsp/fp, m37480e8t-xxxsp/fp, m37481e8-xxxsp/fp, m37481e8t-xxxsp/fp, m37481e8ss pin description table 5. pin description v cc , v ss av ss (note 1) v ref _____ reset p0 0 C p0 7 p1 0 C p1 7 p2 0 C p2 7 (note 2) p3 0 C p3 3 p4 0 C p4 3 (note 3) p5 0 C p5 3 (note 4) single-chip/ eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom single-chip eprom power source reference power input mode input reset input reset input i/o port p0 data i/o d 0 C d 7 i/o port p1 address input a 4 C a 10 input port p2 address input a 0 C a 3 input port p3 address input a 11 , a 12 , mode input, v pp input i/o port p4 address input a 13 , a 14 i/o port p5 input port p5 apply a voltage of 2.7 to 5.5 v to v cc and 0 v to v ss and av ss . reference voltage input pin for a-d converter. __ used as ce input pin. reset input pin. connect to v ss . these are i/o pins of internal clock generating circuit for the main clock. to control generating frequency, an external ceramic resona- tor is connected between x in and x out pins. if an external clock is used, the clock oscillation source should be connected to the x in pin, and the x out pin should be left open. feedback resistor is con- nected between x in and x out . 8-bit i/o port. the output structure is cmos output. when this port is selected for input, a pull-up transistor can be con- nected in units of 1 bit, and a key-on wake-up function is provided. data 8-bit (d 0 to d 7 ) i/o pins 8-bit i/o port. the output structure is cmos output. when this port is selected for input, a pull-up transistor can be con- nected in units of 4 bits. p1 2 and p1 3 are in common with timer output pins t 0 and t 1 . p1 4 , p1 5 , p1 6 and p1 7 are in common with ____ serial i/o pins rxd, txd, s clk and s rdy . p1 1 to p1 7 are address (a 4 to a 10 ) input pins. leave p1 0 open. 8-bit input port. this port is in common with analog input pins in 0 to in 7 (in 0 to in 3 for the 7480 group). p2 0 to p2 3 are address (a 0 to a 3 ) input pins. leave p2 4 to p2 7 open. 4-bit input port. p3 0 and p3 1 are in common with external interrupt input pins int 0 and int 1 . __ p3 0 and p3 1 are address (a 11 , a 12 ) input pins. p3 2 is used for oe input. p3 3 is v pp input. apply v pp in the program and program verify modes. 4-bit i/o port. the output structure is n-channel open drain output, having built-in clamp diode. p4 0 and p4 1 are in common with timer input pins cntr 0 and cntr 1 . p4 0 and p4 1 are address (a 13 , a 14 ) input pins. leave p4 2 and p4 3 open. 4-bit i/o port. the output structure is n-channel open drain output, having a built-in clamp diode. leave these pins open. clock input clock output single-chip/ eprom single-chip/ eprom x in x out notes 1 : this is a dedicated pin for the 44p6n-a package in the 7481 group. 2 : only 4 bits of p2 0 to p2 3 (in 0 to in 3 ) for the 7480 group. 3 : only 2 bits of p4 0 and p4 1 for the 7480 group. 4 : this is a dedicated pin for the 7481 group. input input input input i/o i/o i/o input input input input input i/o input i/o input input output pin function name input/ output mode
47 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. eprom mode the built-in programmable rom has the eprom mode in addition _____ to its normal operation modes. when the reset level becomes l, the chip automatically enters the eprom mode. table 6 shows a list of correspondence between pins and figure 50 to fig- ure 52 show pin connection diagrams. in this status, each of ports p0, p1 1 to p1 7 , p2 0 to p2 3 , p3, p4 0 , p4 1 and v ref are used for the prom (equivalent to m5m27c256k). in this mode, the built-in prom can be written to or read from using these pins in the same way as with the m5m27c256k. the clock should be connected to x in and x out pins. table 6. correspondence between pins in eprom mode m37480e8, m37481e8 v cc p3 3 v ss ports p1 1 C p1 7 , p2 0 C p2 3 , p3 0 , p3 1 , p4 0 , p4 1 port p0 v ref p3 2 v cc v pp v ss address input data i/o __ ce __ oe m5m27c256k v cc v pp v ss a 0 C a 14 d 0 C d 7 __ ce __ oe fig. 50 pin connection in eprom mode (1) outline 42p4b 42s1b-a (m37481e8ss) a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v ss ce d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 14 a 13 v pp a 12 a 11 v cc oe v ss : prom pin (equivalent to m5m27c256k) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 28 29 30 31 32 m37481e8-xxxsp m37481e8t-xxxsp m37481e8ss p1 7 /s rdy p1 6 /s clk p1 5 /t x d p1 4 /r x d p1 3 /t 1 p1 2 /t 0 p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 /cntr 1 p4 0 /cntr 0 p3 3 p3 2 p3 1 /int 1 p3 0 /int 0 reset v cc 17 26 25 24 23 22 18 19 20 21 27 33 35 36 37 38 39 40 41 42 34 p5 3 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p5 2 p5 1 p5 0 p4 3 p4 2
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 48 preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 51 pin connection in eprom mode (2) fig. 52 pin connection in eprom mode (3) outline 44p6n-a : prom pin (equivalent to m5m27c256k) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 28 29 30 31 32 26 25 24 23 27 33 35 36 37 38 39 40 41 42 34 43 44 p1 3 /t 1 p1 2 /t 0 p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 7 /in 7 p2 6 /in 6 p2 5 /in 5 p2 4 /in 4 p2 0 /in 0 v ref x in x out v ss av ss p3 0 /int 0 reset v cc p5 1 p5 0 p0 2 p0 1 p0 0 p4 1 /cntr 1 p4 0 /cntr 0 p3 3 p3 2 p3 1 /int 1 p4 3 p4 2 p0 7 p0 6 p0 5 p0 4 p5 2 p1 7 /s rdy p1 6 /s clk p1 5 /t x d p1 4 /r x d p5 3 v ss m37481e8-xxxfp m37481e8t-xxxfp a 4 p0 3 a 14 a 13 v pp a 12 a 5 a 6 a 1 a 2 a 3 d 2 d 1 d 0 oe d 3 d 4 d 5 d 6 d 7 v ss a 10 a 9 a 8 a 7 a 11 v ss v cc v ss a 0 ce a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v ss ce d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 14 a 13 v pp a 12 a 11 v cc oe v ss : prom pin (equivalent to m5m27c256k) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m37480e8-xxxsp/fp m37480e8t-xxxsp/fp p1 7 /s rdy p1 6 /s clk p1 5 /t x d p1 4 /r x d p1 3 /t 1 p1 2 /t 0 p1 1 p1 0 p2 3 /in 3 p2 2 /in 2 p2 1 /in 1 p2 0 /in 0 v ref x in x out v ss p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p4 1 /cntr 1 p4 0 /cntr 0 p3 3 p3 2 p3 1 /int 1 p3 0 /int 0 reset v cc outline 32p4b 32p2w-a
49 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. the screening temperature is up to 150 c. never expose to 150 c exceeding 100 hours. the m37480e8sp/fp, m37481e8sp/fp and m37481e8ss are not t versions (mountable on vehicles), so it is impossible to mount them on vehicles. the m37481e8ss is for user program evaluation, so it is impossible to mount it on vehicles or on users mass-production real machines. writing with prom programmer screening (leave at 150 c for 40 hours.) (note) verify test with prom programmer function check in target device note : functional description of prom version reading __ __ to read the prom, set the ce and oe pins to l level, and set the address signal (a 0 to a 14 ). the stored contents will appear to __ __ data i/o pins (d 0 to d 7 ). when the ce and oe pins are set to h level, the data i/o pins will be put into a floating status. writing __ to write to the prom, apply h to the oe pin and v pp to the v pp pin to set the program mode. select addresses to be written to with address input pins (a 0 to a 14 ) and give write data to the data input pins (d 0 to d 7 ) in 8-bit parallel form. in this status, when the __ ce pin becomes l, writing will be started. notes on writing when using a prom programmer, specify the address range to address 4000 16 to address 7fff 16 . when data is written between address 0000 16 and address 7fff 16 , fill addresses 0000 16 to 3fff 16 with ff 16 . erasing data can be erased only on the ceramic package with window m37481e8ss. to erase data on this chip, use an ultraviolet light source with a 2537 angstrom wave length. the minimum radiation power required for erasing is 15ws/cm 2 . notes on handling (1) sunlight and fluorescent light contain wavelengths capable of erasing data. for use in the read mode, be sure to cover the transparent window with a seal. (ceramic package type) (2) we can supply the seal with which the transparent window is covered. be careful not to allow the seal to contact the micro- computer lead pins. (ceramic package type) (3) before erasing, clean the transparent glass. if the glass is smeared with greasy hands or paste, ultraviolet light transmis- sion will be prevented, having a negative effect on erasing characteristics. (ceramic package type) (4) since a high voltage is used for writing data, care should be taken not to apply an overvoltage when turning on the power source. (5) for the programmable microcomputers (one-time program- mable version, version shipped in blank), mitsubishi does not perform prom write testing and screening in the assembly process and subsequent processes. to improve reliability after writing, perform writing and testing according to the following operation flow before use. fig. 53 writing and testing for one-time programmable version
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 50 preliminar y notice: this is not a final specification. some parametric limits are subject to change. i/o signals in each mode table 7. i/o signals in each mode read-out output disable programming programming verify program disable output floating input output floating v il v ih v ih v il v ih v cc v cc v pp v pp v pp v cc v cc v cc v cc v cc v il v il v il v ih v ih pin mode __ ce __ oe v pp v cc data i/o note : v il and v ih denote an l input voltage and an h input voltage, respectively.
51 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. tents of the processor status register. data required for mask ordering please submit the following data when placing mask orders. (1) mask rom confirmation form (2) mark specification form (3) rom data .......................................................... eprom 3 sets data required for rom writing ordering please submit the following data when placing rom writing or- ders. (1) rom writing confirmation form (2) mark specification form (3) rom data .......................................................... eprom 3 sets addressing modes the 7480/7481 group has strong accessability, because it has 17 kinds of addressing modes. for details, refer to the 740 family ad- dressing modes. machine-language instructions the 7480/7481 group has 71 machine-language instructions. for details, refer to the 740 family machine-language instruction list. notes on programming (1) the frequency division ratio of the timer is 1/(n+1). n: timer setting value however, n = 0 C 255 (for timer 1, timer 2) n = 0 C 65535 (timer x, timer y) (2) the contents of the interrupt request bits can be changed by software, but the values will not change immediately after be- ing overwritten. after changing the value of the interrupt request bits, execute at least one instruction before executing a the bbc or bbs in- struction. (3) to calculate in decimal notation, set the decimal mode flag (d) to 1. after executing the adc or sbc instruction, execute another instruction before executing the sec, clc, or cld in- struction. (4) a nop instruction should be executed after every plp instruc- tion. (5) do not execute the stp instruction during a-d conversion. (6) multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instructions. the execution of these instructions does not change the con-
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 52 preliminar y notice: this is not a final specification. some parametric limits are subject to change. power source voltage power source voltage h input voltage p0 0 C p0 7 , p1 0 C p1 7 h input voltage p2 0 C p2 3 h input voltage p3 0 C p3 3 h input voltage p4 0 C p4 1 (note 4) _____ h input voltage x in , reset l input voltage p0 0 C p0 7 , p1 0 C p1 7 l input voltage p2 0 C p2 3 l input voltage p3 0 C p3 3 l input voltage p4 0 C p4 1 l input voltage x in _____ l input voltage reset input current p4 0 C p4 1 (note 4) v i > v cc h sum output current p0 0 C p0 7 h sum output current p1 0 C p1 7 l sum output current p0 0 C p0 7 , p4 0 C p4 1 l sum output current p1 0 C p1 7 h peak output current p0 0 C p0 7 , p1 0 C p1 7 l peak output current p0 0 C p0 7 , p1 0 C p1 7 , p4 0 C p4 1 h average output current p0 0 C p0 7 , p1 0 C p1 7 (note 2) l average output current p0 0 C p0 7 , p1 0 C p1 7 , p4 0 C p4 1 (note 2) m37480m4/m8/e8-xxxsp/fp, m37480m2t/m4t/m8t/e8t-xxxsp/fp absolute maximum ratings (7480 group) table 8. absolute maximum ratings v v v mw c c v cc v i v o p d t opr t stg power source voltage input voltage output voltage power dissipation operating temperature range storage temperature C0.3 to 7 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 1000 (note 1) C20 to 85 (note 2) C40 to 150 (note 3) unit symbol parameter condition rated value all voltages are measured on the basis of the v ss pin. output transistors are cut off. t a = 25 c notes 1 : 500 mw for 32p2w-a package type. 2 : C40 to 85 c for extended operating temperature range version. 3 : C65 to 150 c for extended operating temperature range version. recommended operating conditions (7480 group) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85c (note 1) unless otherwise specified) table 9. recommended operating conditions 2.7 4.5 0.8 v cc 0.7 v cc 0.8 v cc 0.9 v cc 0.8 v cc 0.9 v cc 0.8 v cc 0 0 0 0 0 0 0 0 v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma ma ma ma 4.5 5.5 v cc v cc v cc v cc v cc v cc v cc 0.2 v cc 0.25 v cc 0.4 v cc 0.3 v cc 0.4 v cc 0.3 v cc 0.16 v cc 0.12 v cc 1 C 30 C 30 60 60 C 10 20 C 5 10 3 5 0 v cc v ss v ih v ih v ih v ih v ih v il v il v il v il v il v il i i i oh(sum) i oh(sum) i ol(sum) i ol(sum) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(x in ) = (2.2v cc C 2) mhz f(x in ) = 8 mhz v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v symbol parameter standard values min. typ. max. unit
53 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 9. recommended operating conditions (cont.) symbol parameter standard values min. typ. max. unit 1 2 250 500 1 2 2.2v cc C2 8 f(cntr) f(s clk ) f(x in ) f(x in ) = 4 mhz f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v mhz khz mhz mhz timer input frequency cntr 0 (p4 0 ), cntr 1 (p4 1 ) (note 3) clock input oscillation frequency (note 3) serial i/o clock input frequency s clk (p1 6 ) (note 3) clock synchronous serial i/o mode uart mode notes 1 : C40 to 85 c for extended operating temperature range version. 2 : the average output currents i oh (avg) and i ol (avg) are the average values during 100 ms. 3 : the clock input oscillation frequency is at 50 % duty ratio. 4 : when applying a voltage through a resistor as shown in the figure 54, v i > v cc may be accepted if the current is 1 ma or less. fig. 54 note on use of port p4 notes on clamp diode (7480 group) (1) total input current the current of port p4 through the clamp diode can be drawn up to 1.0 ma per port. when a current that cannot be con- sumed by microcomputer is sent to the clamp diode, this may raise the power source pin voltage of the microcomputer. the system power circuit must be designed so that the power source voltage of the microcomputer may be stabilized within standard values. (2) maximum input voltage if the input voltage of a signal connected to port p4 is beyond v cc + 0.3 v, the input waveform should have a delay exceed- ing 2 s/v from the moment that this waveform goes over the voltage. for using a cr circuit for delay, calculate a proper delay value by the following expression: where v in = maximum input voltage amplitude margin and t = c 5 r. dt dv =3 2 5 10 C6 (s/v) t 0.6 5 v in port p4 i vi the clamp diode of the 7480/7481 group is designed for a level shift of dc signal unlike ordinary switching diodes. do not apply sudden stress, such as rush current, directly to the diode. notes on countermeasures for noise and latch-up (7480 group) (1) connect a bypass capacitor (0.1 f) across the v cc pin and the v ss pin with the shortest possible wiring, using a relatively thick wire. (2) connect a bypass capacitor (0.01 f) across the v ref pin and the v ss pin with the shortest possible wiring, using a relatively thick wire. (3) in the oscillation circuit, connect across the x in and x out pins with the shortest possible wiring. connect the gnd and v ss pins of the oscillation circuit with the shortest possible wiring, using a relatively thick wire. (4) in the case of the p3 3 /v pp pin of the built-in programmable rom version, connect an approximately 5 k w resistor to the p3 3 /v pp pin the shortest possible in series.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 54 preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37480m4/m8/e8-xxxsp/fp, m37480m2t/m4t/m8t/e8t-xxxsp/fp electrical characteristics (7480 group) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c (note 1) unless otherwise specified) notes 1 : C40 to 85 c for extended operating temperature range version. 2 : at using p0 for key-on wake-up function. 3 : can be indicated in resistance value as shown below: when v cc = 5 v: 5 k w (min.), 10 k w (typ.), 20 k w (max.). when v cc = 3 v: 8.6 k w (min.), 16.7 k w (typ.), 37.5 k w (max.). max. standard values symbol parameter min. typ. unit table 10. electrical characteristics v oh v ol v t+ C v tC v t+ Cv tC v t+ Cv tC i ih i ih i ih i ih i il i il i il i il 2 1 5 3 5 3 5 3 5 3 C5 C3 C1.0 C0.35 C5 C3 C5 C3 C5 C3 0.5 0.3 0.5 0.3 0.5 0.3 C0.5 C0.18 h output voltage p0 0 C p0 7 , p1 0 C p1 7 l output voltage p0 0 C p0 7 , p1 0 C p1 7 , p4 0 C p4 1 hysteresis p0 0 C p0 7 , p3 0 C p3 3 , p4 0 C p4 1 (note 2) hysteresis p1 6 /s clk , p1 4 /r x d _____ hysteresis reset h input current p0 0 C p0 7 , p1 0 C p1 7 h input current p3 0 C p3 3 , p4 0 C p4 1 h input current p2 0 C p2 3 _____ h input current reset, x in l input current p0 0 C p0 7 , p1 0 C p1 7 l input current p3 0 C p3 3 , p4 0 C p4 1 l input current p2 0 C p2 3 _____ l input current reset, x in v v v v v a a a a a ma a a a test conditions v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v 3 2 C0.25 C0.08 v cc = 5 v, i oh = C5 ma v cc = 3 v, i oh = C1.5 ma v cc = 5 v, i ol = 10 ma v cc = 3 v, i ol = 3 ma v cc = 5 v v cc = 3 v when used as s clk , rxd input v cc = 5 v v cc = 3 v v i = v cc without pull-up transistor v i = v cc = 5 v v i = v cc = 3 v v i = v cc when analog input is not selected v i = v cc (x in at stop) v i = 0 v without pull-up transistor v i = 0 v with pull-up transistor (note 3) v i = 0 v v i = 0 v when analog input is not selected v i = 0 v (x in at stop)
55 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress v cc = 5 v v cc = 3 v v cc = 5 v v cc = 5 v v cc = 3 v v cc = 5 v t a = 25 c t a = 85 c m37480m4/m8/e8-xxxsp/fp, m37480m2t/m4t/m8t/e8t-xxxsp/fp table 10. electrical characteristics (cont.) max. standard values symbol parameter min. typ. unit test conditions 7 8 3.6 4 14 15 3.5 4 1.8 2 7 7.5 2 1 4 1.8 0.9 3.6 1 10 v ram i cc v ma ma ma ma ma ma ma ma ma ma ma ma ma ma a a 2 3.5 4 1.8 2 7 7.5 1.75 2 0.9 1 3.5 3.75 1 0.5 2 0.9 0.45 1.8 0.1 1 in operating mode in wait mode in stop mode in high-speed mode, f(x in ) = 4 mhz, v cc = 5 v in high-speed mode, f(x in ) = 4 mhz, v cc = 3 v in high-speed mode, f(x in ) = 8 mhz, v cc = 5 v in medium-speed mode, f(x in ) = 4 mhz, v cc = 5 v in medium-speed mode, f(x in ) = 4 mhz, v cc = 3 v in medium-speed mode, f(x in ) = 8 mhz, v cc = 5 v in high-speed mode, f(x in ) = 4 mhz in high-speed mode, f(x in ) = 8 mhz in medium-speed mode, f(x in ) = 4 mhz in medium-speed mode, f(x in ) = 8 mhz f(x in ) = 0 v cc = 5 v ram retention voltage power source current at clock stop mode
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 56 preliminar y notice: this is not a final specification. some parametric limits are subject to change. unit symbol parameter test conditions standard values t conv v vref r ladder v ia i vref 8 2 25 12.5 v cc v cc 100 v ref 416 bits lsb s v k w v a resolution absolute accuracy (except quantization error) conversion time reference voltage ladder resistance analog input voltage reference input current v cc = v ref = 5.0 v v cc = 2.7 to 5.5 v, f(x in ) = 4 mhz v cc = 4.5 to 5.5 v, f(x in ) = 8 mhz v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v ref = 5.0 v m37480m4/m8/e8-xxxsp/fp, m37480m2t/m4t/m8t/e8t-xxxsp/fp a-d conversion characteristics (7480 group) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c (note) unless otherwise specified) table 11. a-d conversion characteristics 2 0.5 v cc 12 0 50 35 143 max. ty p. min. note: C40 to 85 c for extended operating temperature range version.
57 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. power source voltage power source voltage h input voltage p0 0 C p0 7 , p1 0 C p1 7 h input voltage p2 0 C p2 7 h input voltage p3 0 C p3 3 h input voltage p4 0 C p4 3 , p5 0 C p5 3 (note 4) _____ h input voltage x in , reset l input voltage p0 0 C p0 7 , p1 0 C p1 7 l input voltage p2 0 C p2 7 l input voltage p3 0 C p3 3 l input voltage p4 0 C p4 3 , p5 0 C p5 3 l input voltage x in _____ l input voltage reset input current p4 0 C p4 3 , p5 0 C p5 3 (note 4) v i > v cc h sum output current p0 0 C p0 7 h sum output current p1 0 C p1 7 l" sum output current p0 0 C p0 7 , p4 0 C p4 3 , p5 0 C p5 2 l sum output current p1 0 C p1 7 , p5 3 h peak output current p0 0 C p0 7 , p1 0 C p1 7 l peak output current p0 0 C p0 7 , p1 0 C p1 7 , p4 0 C p4 3 , p5 0 C p5 3 h average output current p0 0 C p0 7 , p1 0 C p1 7 (note 2) l average output current p0 0 C p0 7 , p1 0 C p1 7 , p4 0 C p4 3 , p5 0 C p5 3 (note 2) m37481m4/m8/e8-xxxsp/fp, m37481m2t/m4t/m8t/e8t-xxxsp/fp, m37481e8ss absolute maximum ratings (7481 group) table 12. absolute maximum ratings v v v mw c c v cc v i v o p d t opr t stg power source voltage input voltage output voltage power dissipation operating temperature range storage temperature C0.3 to 7 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 1000 (note 1) C20 to 85 (note 2) C40 to 150 (note 3) unit symbol parameter condition rated value all voltages are measured on the basis of the v ss pin. output transistors are cut off. t a = 25 c notes 1 : 500 mw for 44p6n-a package type. 2 : C40 to 85 c for extended operating temperature range version. 3 : C65 to 150 c for extended operating temperature range version. recommended operating conditions (7481 group) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85c (note 1) unless otherwise specified) table 13. recommended operating conditions 2.7 4.5 0.8 v cc 0.7 v cc 0.8 v cc 0.9 v cc 0.8 v cc 0.9 v cc 0.8 v cc 0 0 0 0 0 0 0 0 v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma ma ma ma 4.5 5.5 v cc v cc v cc v cc v cc v cc v cc 0.2 v cc 0.25 v cc 0.4 v cc 0.3 v cc 0.4 v cc 0.3 v cc 0.16 v cc 0.12 v cc 1 C30 C30 60 60 C10 20 C5 10 3 5 0 v cc v ss v ih v ih v ih v ih v ih v il v il v il v il v il v il i i i oh(sum) i oh(sum) i ol(sum) i ol(sum) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(x in ) = (2.2v cc C 2) mhz f(x in ) = 8 mhz v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v symbol parameter standard values min. typ. max. unit
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 58 preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 13. recommended operating conditions (cont.) symbol parameter standard values min. typ. max. unit 1 2 250 500 1 2 2.2v cc C2 8 f(cntr) f(s clk ) f(x in ) f(x in ) = 4 mhz f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz f(x in ) = 4 mhz f(x in ) = 8 mhz v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v mhz khz mhz mhz timer input frequency cntr 0 (p4 0 ), cntr 1 (p4 1 ) (note 3) clock input oscillation frequency (note 3) serial i/o clock input frequency s clk (p1 6 ) (note 3) clock synchronous serial i/o mode uart mode notes 1 : C40 to 85 c for extended operating temperature range version. 2 : the average output currents i oh (avg) and i ol (avg) are the average values during 100 ms. 3 : the clock input oscillation frequency is at 50 % duty ratio. 4 : when applying a voltage through a resistor as shown in the figure 55, v i > v cc may be accepted if the current is 1 ma or less. fig. 55 notes on use of ports p4 and p5 notes on clamp diode (7481 group) (1) total input current the current of ports p4 and p5 through the clamp diode can be drawn up to 1.0 ma per port. when a current that cannot be consumed by microcomputer is sent flow to the clamp diode, this may raise the power source pin voltage of the microcom- puter. the system power circuit must be designed so that the power source voltage of the microcomputer may be stabilized within the standard values. (2) maximum input voltage if the input voltage of a signal connected to ports p4 and p5 is beyond v cc + 0.3 v, the input waveform should have a delay exceeding 2 s/v from the moment that this waveform goes over the voltage. for using a cr circuit for delay, calculate a proper delay value by the following expression: where v in = maximum input voltage amplitude margin and t = c 5 r. dt dv =3 2 5 10 C6 (s/v) t 0.6 5 v in port p4, p5 i vi the clamp diode of the 7480/7481 group is designed for a level shift of dc signal unlike ordinary switching diodes. do not apply sudden stress, such as rush current, directly to the diode. notes on countermeasures for noise and latch-up (7481 group) (1) connect a bypass capacitor (0.1 f) across the v cc pin and the v ss pin with the shortest possible wiring, using a relatively thick wire. (2) connect a bypass capacitor (0.01 f) across the v ref pin and the v ss pin with the shortest possible wiring, using a relatively thick wire. (3) in the oscillation circuit, connect across the x in and x out pins with the shortest possible wiring. connect the gnd and v ss pins of the oscillation circuit with the shortest possible wiring, using a relatively thick wire. (4) in the case of the p3 3 /v pp pin of the built-in programmable rom version, connect an approximately 5 k w resistor to the p3 3 /v pp pin the shortest possible in series.
59 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481m4/m8/e8-xxxsp/fp, m37481m2t/m4t/m8t/e8t-xxxsp/fp, m37481e8ss electrical characteristics (7481 group) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c (note 1) unless otherwise specified) v cc = 5 v, i oh = C5 ma v cc = 3 v, i oh = C1.5 ma v cc = 5 v, i ol = 10 ma v cc = 3 v, i ol = 3 ma v cc = 5 v v cc = 3 v when used as s clk , rxd input v cc = 5 v v cc = 3 v v i = v cc without pull-up transistor v i = v cc = 5 v v i = v cc = 3 v v i = v cc when analog input is not selected v i = v cc (x in at stop) v i = 0 v without pull-up transistor v i = 0 v with pull-up transistor (note 3) v i = 0 v v i = 0 v when analog input is not selected v i = 0 v (x in at stop) max. standard values symbol parameter min. typ. unit table 14. electrical characteristics v oh v ol v t+ C v tC v t+ Cv tC v t+ Cv tC i ih i ih i ih i ih i il i il i il i il 2 1 5 3 5 3 5 3 5 3 C5 C3 C1.0 C0.35 C5 C3 C5 C3 C5 C3 0.5 0.3 0.5 0.3 0.5 0.3 C0.5 C0.18 3 2 C0.25 C0.08 h output voltage p0 0 C p0 7 , p1 0 C p1 7 l output voltage p0 0 C p0 7 , p1 0 C p1 7 , p4 0 C p4 3 , p5 0 C p5 3 hysteresis p0 0 C p0 7 , (note 2) p3 0 C p3 3 , p4 0 C p4 3 , p5 0 C p5 3 hysteresis p1 6 /s clk , p1 4 /r x d _____ hysteresis reset h input current p0 0 C p0 7 , p1 0 C p1 7 h input current p3 0 C p3 3 , p4 0 C p4 3 , p5 0 C p5 3 h input current p2 0 C p2 7 _____ h input current reset, x in l input current p0 0 C p0 7 , p1 0 C p1 7 l input current p3 0 C p3 3 , p4 0 C p4 3 , p5 0 C p5 3 l input current p2 0 C p2 7 _____ l input current reset, x in v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v cc = 5 v v cc = 3 v v v v v v a a a a a ma a a a notes 1 : C40 to 85 c for extended operating temperature range version. 2 : using p0 for key-on wake-up function. 3 : can be indicated in resistance value as shown below: when v cc = 5 v: 5 k w (min.), 10 k w (typ.), 20 k w (max.). when v cc = 3 v: 8.6 k w (min.), 16.7 k w (typ.), 37.5 k w (max.). test conditions
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 60 preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress a-d conversion not executed a-d conversion in progress v cc = 5 v v cc = 3 v v cc = 5 v v cc = 5 v v cc = 3 v v cc = 5 v t a = 25 c t a = 85 c m37481m4/m8/e8-xxxsp/fp, m37481m2t/m4t/m8t/e8t-xxxsp/fp, m37481e8ss table 14. electrical characteristics (cont.) max. standard values symbol parameter min. typ. unit test conditions 7 8 3.6 4 14 15 3.5 4 1.8 2 7 7.5 2 1 4 1.8 0.9 3.6 1 10 v ram i cc v ma ma ma ma ma ma ma ma ma ma ma ma ma ma a a 2 3.5 4 1.8 2 7 7.5 1.75 2 0.9 1 3.5 3.75 1 0.5 2 0.9 0.45 1.8 0.1 1 in operating mode in wait mode in stop mode in high-speed mode, f(x in ) = 4 mhz, v cc = 5 v in high-speed mode, f(x in ) = 4 mhz, v cc = 3 v in high-speed mode, f(x in ) = 8 mhz, v cc = 5 v in medium-speed mode, f(x in ) = 4 mhz, v cc = 5 v in medium-speed mode, f(x in ) = 4 mhz, v cc = 3 v in medium-speed mode, f(x in ) = 8 mhz, v cc = 5 v in high-speed mode, f(x in ) = 4 mhz in high-speed mode, f(x in ) = 8 mhz in medium-speed mode, f(x in ) = 4 mhz in medium-speed mode, f(x in ) = 8 mhz f(x in ) = 0 v cc = 5 v ram retention voltage power source current at clock stop mode
61 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. unit symbol parameter test conditions standard values t conv v vref r ladder v ia i vref 8 2 25 12.5 v cc v cc 100 v ref 416 bits lsb s v k w v a resolution absolute accuracy (except quantization error) conversion time reference voltage ladder resistance analog input voltage reference input current v cc = v ref = 5.0 v v cc = 2.7 to 5.5 v, f(x in ) = 4 mhz v cc = 4.5 to 5.5 v, f(x in ) = 8 mhz v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v ref = 5.0 v 2 0.5 v cc 12 0 50 35 143 max. ty p . min. note: C40 to 85 c for extended operating temperature range version. m37481m4/m8/e8-xxxsp/fp, m37481m2t/m4t/m8t/e8t-xxxsp/fp, m37481e8ss a-d conversion characteristics (7481 group) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85c (note) unless otherwise specified) table 15. a-d conversion characteristics
62 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor m37480m2t-xxxsp gzz-sh09-84b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37480m2t-xxxsp/fp mitsubishi electric microcomputer name : 27128 27256 0000 16 000f 16 0010 16 2fff 16 3000 16 3fff 16 checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37480m2tC to addresses 0000 16 to 000f 16 . ascii codes m37480m2tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 0 = 30 16 m = 4d 16 2 = 32 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom address eprom type (indicate the type used) microcomputer name : m37480m2t-xxxfp 27512 0000 16 000f 16 0010 16 6fff 16 7000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 efff 16 f000 16 ffff 16 eprom address area for ascii codes of the name of the product m37480m2tC area for ascii codes of the name of the product m37480m2t- area for ascii codes of the name of the product m37480m2tC rom (4k) rom (4k) rom (4k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. mask rom confirmation form
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 63 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 740 family mask rom confirmation form single-chip microcomputer m37480m2t-xxxsp/fp mitsubishi electric gzz-sh09-84b<56a0> recommend to writing the following pseudo-command to the start address of the assembler source program. note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32p4b for m37480m2t-xxxsp, 32p2w-a for m37480m2t-xxxfp) and attach to the mask rom confirmation form. 27256 27512 ] = $8000 .byte m37480m2tC ] = $0000 .byte m37480m2tC 27128 ] = $c000 .byte m37480m2tC eprom type the pseudo-command h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 64 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37480m4-xxxsp gzz-sh09-85b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37480m4-xxxsp/fp mitsubishi electric microcomputer name : 27128 27256 0000 16 000f 16 0010 16 1fff 16 2000 16 3fff 16 checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37480m4C to addresses 0000 16 to 000f 16 . ascii codes m37480m4C are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 0 = 30 16 m = 4d 16 4 = 34 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom address eprom type (indicate the type used) microcomputer name : m37480m4-xxxfp 27512 0000 16 000f 16 0010 16 5fff 16 6000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 dfff 16 e000 16 ffff 16 eprom address area for ascii codes of the name of the product m37480m4C area for ascii codes of the name of the product m37480m4- area for ascii codes of the name of the product m37480m4C rom (8k) rom (8k) rom (8k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 65 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 740 family mask rom confirmation form single-chip microcomputer m37480m4-xxxsp/fp mitsubishi electric gzz-sh09-85b<56a0> recommend to writing the following pseudo-command to the start address of the assembler source program. note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32p4b for m37480m4-xxxsp, 32p2w-a for m37480m4-xxxfp) and attach to the mask rom confirmation form. 27256 27512 ] = $8000 .byte m37480m4C ] = $0000 .byte m37480m4C 27128 ] = $c000 .byte m37480m4C eprom type the pseudo-command h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 66 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37480m4t-xxxsp gzz-sh09-86b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37480m4t-xxxsp/fp mitsubishi electric microcomputer name : 27128 27256 0000 16 000f 16 0010 16 1fff 16 2000 16 3fff 16 checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37480m4tC to addresses 0000 16 to 000f 16 . ascii codes m37480m4tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 0 = 30 16 m = 4d 16 4 = 34 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom address eprom type (indicate the type used) microcomputer name : m37480m4t-xxxfp 27512 0000 16 000f 16 0010 16 5fff 16 6000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 dfff 16 e000 16 ffff 16 eprom address area for ascii codes of the name of the product m37480m4tC area for ascii codes of the name of the product m37480m4t- area for ascii codes of the name of the product m37480m4tC rom (8k) rom (8k) rom (8k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 67 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 740 family mask rom confirmation form single-chip microcomputer m37480m4t-xxxsp/fp mitsubishi electric gzz-sh09-86b<56a0> recommend to writing the following pseudo-command to the start address of the assembler source program. note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32p4b for m37480m4t-xxxsp, 32p2w-a for m37480m4t-xxxfp) and attach to the mask rom confirmation form. 27256 27512 ] = $8000 .byte m37480m4tC ] = $0000 .byte m37480m4tC 27128 ] = $c000 .byte m37480m4tC eprom type the pseudo-command h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 68 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37480m8-xxxsp gzz-sh09-87b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37480m8-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37480m8C to addresses 0000 16 to 000f 16 . ascii codes m37480m8C are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 0 = 30 16 m = 4d 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) microcomputer name : m37480m8-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37480m8C area for ascii codes of the name of the product m37480m8C rom (16k) rom (16k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 69 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37480m8- ] = $0000 .byte m37480m8- 740 family mask rom confirmation form single-chip microcomputer m37480m8-xxxsp/fp mitsubishi electric gzz-sh09-87b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32p4b for m37480m8-xxxsp, 32p2w-a for m37480m8-xxxfp) and attach to the mask rom confirmation form. h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 70 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37480m8t-xxxsp gzz-sh09-88b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37480m8t-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37480m8tC to addresses 0000 16 to 000f 16 . ascii codes m37480m8tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 0 = 30 16 m = 4d 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) microcomputer name : m37480m8t-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37480m8tC area for ascii codes of the name of the product m37480m8tC rom (16k) rom (16k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 71 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37480m8t- ] = $0000 .byte m37480m8t- 740 family mask rom confirmation form single-chip microcomputer m37480m8t-xxxsp/fp mitsubishi electric gzz-sh09-88b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32p4b for m37480m8t-xxxsp, 32p2w-a for m37480m8t-xxxfp) and attach to the mask rom confirmation form. h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 72 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481m2t-xxxsp gzz-sh09-78b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37481m2t-xxxsp/fp mitsubishi electric microcomputer name : 27128 27256 0000 16 000f 16 0010 16 2fff 16 3000 16 3fff 16 checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37481m2tC to addresses 0000 16 to 000f 16 . ascii codes m37481m2tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 1 = 31 16 m = 4d 16 2 = 32 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom address eprom type (indicate the type used) microcomputer name : m37481m2t-xxxfp 27512 0000 16 000f 16 0010 16 6fff 16 7000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 efff 16 f000 16 ffff 16 eprom address area for ascii codes of the name of the product m37481m2tC area for ascii codes of the name of the product m37481m2t- area for ascii codes of the name of the product m37481m2tC rom (4k) rom (4k) rom (4k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 73 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 740 family mask rom confirmation form single-chip microcomputer m37481m2t-xxxsp/fp mitsubishi electric gzz-sh09-78b<56a0> recommend to writing the following pseudo-command to the start address of the assembler source program. note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42p4b for m37481m2t-xxxsp, 44p6n-a for m37481m2t-xxxfp) and attach to the mask rom confirmation form. 27256 27512 ] = $8000 .byte m37481m2tC ] = $0000 .byte m37481m2tC 27128 ] = $c000 .byte m37481m2tC eprom type the pseudo-command h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 74 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481m4-xxxsp gzz-sh09-79b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37481m4-xxxsp/fp mitsubishi electric microcomputer name : 27128 27256 0000 16 000f 16 0010 16 1fff 16 2000 16 3fff 16 checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37481m4C to addresses 0000 16 to 000f 16 . ascii codes m37481m4C are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 1 = 31 16 m = 4d 16 4 = 34 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom address eprom type (indicate the type used) microcomputer name : m37481m4-xxxfp 27512 0000 16 000f 16 0010 16 5fff 16 6000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 dfff 16 e000 16 ffff 16 eprom address area for ascii codes of the name of the product m37481m4C area for ascii codes of the name of the product m37481m4- area for ascii codes of the name of the product m37481m4C rom (8k) rom (8k) rom (8k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 75 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 740 family mask rom confirmation form single-chip microcomputer m37481m4-xxxsp/fp mitsubishi electric gzz-sh09-79b<56a0> recommend to writing the following pseudo-command to the start address of the assembler source program. note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42p4b for m37481m4-xxxsp, 44p6n-a for m37481m4-xxxfp) and attach to the mask rom confirmation form. 27256 27512 ] = $8000 .byte m37481m4C ] = $0000 .byte m37481m4C 27128 ] = $c000 .byte m37481m4C eprom type the pseudo-command h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 76 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481m4t-xxxsp gzz-sh09-80b<56a0> microcomputer name : 27128 27256 0000 16 000f 16 0010 16 1fff 16 2000 16 3fff 16 checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37481m4tC to addresses 0000 16 to 000f 16 . ascii codes m37481m4tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 1 = 31 16 m = 4d 16 4 = 34 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom address eprom type (indicate the type used) microcomputer name : m37481m4t-xxxfp 27512 0000 16 000f 16 0010 16 5fff 16 6000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 dfff 16 e000 16 ffff 16 eprom address area for ascii codes of the name of the product m37481m4tC area for ascii codes of the name of the product m37481m4t- area for ascii codes of the name of the product m37481m4tC rom (8k) rom (8k) rom (8k) 740 family mask rom confirmation form single-chip microcomputer m37481m4t-xxxsp/fp mitsubishi electric mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 77 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 740 family mask rom confirmation form single-chip microcomputer m37481m4t-xxxsp/fp mitsubishi electric gzz-sh09-80b<56a0> recommend to writing the following pseudo-command to the start address of the assembler source program. note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42p4b for m37481m4t-xxxsp, 44p6n-a for m37481m4t-xxxfp) and attach to the mask rom confirmation form. 27256 27512 ] = $8000 .byte m37481m4tC ] = $0000 .byte m37481m4tC 27128 ] = $c000 .byte m37481m4tC eprom type the pseudo-command h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 78 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481m8-xxxsp gzz-sh09-81b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37481m8-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37481m8C to addresses 0000 16 to 000f 16 . ascii codes m37481m8C are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 1 = 31 16 m = 4d 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) microcomputer name : m37481m8-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37481m8C area for ascii codes of the name of the product m37481m8C rom (16k) rom (16k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 79 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37481m8- ] = $0000 .byte m37481m8- 740 family mask rom confirmation form single-chip microcomputer m37481m8-xxxsp/fp mitsubishi electric gzz-sh09-81b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42p4b for m37481m8-xxxsp, 44p6n-a for m37481m8-xxxfp) and attach to the mask rom confirmation form. h 3. comments mask rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 80 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481m8t-xxxsp gzz-sh09-82b<56a0> 740 family mask rom confirmation form single-chip microcomputer m37481m8t-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37481m8tC to addresses 0000 16 to 000f 16 . ascii codes m37481m8tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 1 = 31 16 m = 4d 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) microcomputer name : m37481m8t-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37481m8tC area for ascii codes of the name of the product m37481m8tC rom (16k) rom (16k) mask rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 81 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37481m8t- ] = $0000 .byte m37481m8t- 740 family mask rom confirmation form single-chip microcomputer m37481m8t-xxxsp/fp mitsubishi electric gzz-sh09-82b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the mask confirmation, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42p4b for m37481m8t-xxxsp, 44p6n-a for m37481m8t-xxxfp) and attach to the mask rom confirmation form. h 3. comments mask rom number
82 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor m37480e8-xxxsp gzz-sh09-91b<56a0> 740 family rom programming confirmation form single-chip microcomputer m37480e8-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37480e8C to addresses 0000 16 to 000f 16 . ascii codes m37480e8C are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 0 = 30 16 e = 45 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) m37480e8-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37480e8C area for ascii codes of the name of the product m37480e8C rom (16k) rom (16k) rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce rom programming based on this data. we shall assume the responsibility for errors only if the rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. rom programming confirmation form
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 83 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37480e8- ] = $0000 .byte m37480e8- 740 family rom programming confirmation form single-chip microcomputer m37480e8-xxxsp/fp mitsubishi electric gzz-sh09-91b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the rom programming confirmation form, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. please submit the shrink dip package mark specification form (only for built-in one time prom microcomputer) for the m37480e8-xxxsp or the 32p2w-a mark specification form for the m37480e8-xxxfp. h 3. comments rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 84 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37480e8t-xxxsp gzz-sh09-92b<56a0> 740 family rom programming confirmation form single-chip microcomputer m37480e8t-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37480e8tC to addresses 0000 16 to 000f 16 . ascii codes m37480e8tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 0 = 30 16 e = 45 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) microcomputer name : m37480e8t-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37480e8tC area for ascii codes of the name of the product m37480e8tC rom (16k) rom (16k) rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce rom programming based on this data. we shall assume the responsibility for errors only if the rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 85 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37480e8t- ] = $0000 .byte m37480e8t- 740 family rom programming confirmation form single-chip microcomputer m37480e8t-xxxsp/fp mitsubishi electric gzz-sh09-92b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the rom programming confirmation form, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. please submit the shrink dip package mark specification form (only for built-in one time prom microcomputer) for the m37480e8t-xxxsp or the 32p2w-a mark specification form for the m37480e8t-xxxfp. h 3. comments rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 86 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481e8-xxxsp gzz-sh09-89b<56a0> 740 family rom programming confirmation form single-chip microcomputer m37481e8-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37481e8C to addresses 0000 16 to 000f 16 . ascii codes m37481e8C are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 1 = 31 16 e = 45 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) m37481e8-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37481e8C area for ascii codes of the name of the product m37481e8C rom (16k) rom (16k) rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce rom programming based on this data. we shall assume the responsibility for errors only if the rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 87 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37481e8- ] = $0000 .byte m37481e8- 740 family rom programming confirmation form single-chip microcomputer m37481e8-xxxsp/fp mitsubishi electric gzz-sh09-89b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the rom programming confirmation form, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. please submit the shrink dip package mark specification form (only for built-in one time prom microcomputer) for the m37481e8-xxxsp or the 44p6n-a mark specification form for the m37481e8-xxxfp. h 3. comments rom number
receipt date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor 88 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. m37481e8t-xxxsp gzz-sh09-90b<56a0> 740 family rom programming confirmation form single-chip microcomputer m37481e8t-xxxsp/fp mitsubishi electric microcomputer name : checksum code for entire eprom (hexadecimal notation) (1) set ff 16 in the shaded area. (2) write the ascii codes that indicates the name of the product m37481e8tC to addresses 0000 16 to 000f 16 . ascii codes m37481e8tC are listed on the right. the addresses and data are in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 7 = 37 16 4 = 34 16 8 = 38 16 1 = 31 16 e = 45 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t = 54 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 eprom type (indicate the type used) microcomputer name : m37481e8t-xxxfp 27256 27512 0000 16 000f 16 0010 16 3fff 16 4000 16 7fff 16 eprom address 0000 16 000f 16 0010 16 bfff 16 c000 16 ffff 16 eprom address area for ascii codes of the name of the product m37481e8tC area for ascii codes of the name of the product m37481e8tC rom (16k) rom (16k) rom number h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern (check @ in the appropriate box). if at least two of the three sets of eproms submitted contain identical data, we will produce rom programming based on this data. we shall assume the responsibility for errors only if the rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms.
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 89 preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] = $8000 .byte m37481e8t- ] = $0000 .byte m37481e8t- 740 family rom programming confirmation form single-chip microcomputer m37481e8t-xxxsp/fp mitsubishi electric gzz-sh09-90b<56a0> recommend to writing the following pseudo-command to the assembler source file : 27256 27512 eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the rom programming confirmation form, the rom processing is disabled. write the data correctly. h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. please submit the shrink dip package mark specification form (only for built-in one time prom microcomputer) for the m37481e8t-xxxsp or the 44p6n-a mark specification form for the m37481e8t-xxxfp. h 3. comments rom number
90 mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change. package outline 32p2wCa 32p4b
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 91 preliminar y notice: this is not a final specification. some parametric limits are subject to change. 42p4b 44p6nCa
9 2 m i t s u b i s h i m i c r o c o m p u t e r s 7 4 8 0 / 7 4 8 1 g r o u p s i n g l e - c h i p 8 - b i t c m o s m i c r o c o m p u t e r p r e l i m i n a r y n o t i c e : t h i s i s n o t a f i n a l s p e c i f i c a t i o n . s o m e p a r a m e t r i c l i m i t s a r e s u b j e c t t o c h a n g e . 3 2 p 4 b ( 3 2 - p i n s h r i n k d i p ) m a r k s p e c i f i c a t i o n f o r m m a r k s p e c i f i c a t i o n f o r m
m i t s u b i s h i m i c r o c o m p u t e r s 7 4 8 0 / 7 4 8 1 g r o u p s i n g l e - c h i p 8 - b i t c m o s m i c r o c o m p u t e r 9 3 p r e l i m i n a r y n o t i c e : t h i s i s n o t a f i n a l s p e c i f i c a t i o n . s o m e p a r a m e t r i c l i m i t s a r e s u b j e c t t o c h a n g e . 3 2 p 2 w ( 3 2 - p i n s o p ) m a r k s p e c i f i c a t i o n f o r m
9 4 m i t s u b i s h i m i c r o c o m p u t e r s 7 4 8 0 / 7 4 8 1 g r o u p s i n g l e - c h i p 8 - b i t c m o s m i c r o c o m p u t e r p r e l i m i n a r y n o t i c e : t h i s i s n o t a f i n a l s p e c i f i c a t i o n . s o m e p a r a m e t r i c l i m i t s a r e s u b j e c t t o c h a n g e . 4 2 p 4 b ( 4 2 - p i n s h r i n k d i p ) m a r k s p e c i f i c a t i o n f o r m
mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer 95 preliminar y notice: this is not a final specification. some parametric limits are subject to change. mitsubishi ic catalog name a. standard mitsubishi mark note1 : if the special mark is to be printed, indicate the desired layout of the mark in the left figure. the layout will be duplicated as close as possible. mitsubishi lot number (6-digit ) and mask rom number (3-digit) are always marked. 2 : if the customers trade mark logo must be used in the special mark, check the box below. please submit a clean original of the logo. for the new special character fonts a clean font original (ideally logo drawing) must be sub- mitted. 44p6n (44-pin qfp) mark specification form q!1 #3 @3 !2 @2 $4 #4 mitsubishi lot number (6-digit) mitsubishi ic catalog name 3 : the standard mitsubishi font is used for all characters ex- cept for a logo. special logo required please choose one of the marking types below (a, b, c), and enter the mitsubishi ic catalog name and the special mark (if needed). q!1 #3 @3 !2 @2 $4 #4 mitsubishi ic catalog name and mitsubishi lot number note4 : if the mitsubishi logo is not required, check the box below. mitsubishi logo is not required. customer? parts number note : the fonts and size of characters are standard mitsubishi type. b. customers parts number + mitsubishi catalog name q!1 #3 @3 !2 @2 $4 #4 c. special mark required note1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 7 characters : only 0 ~ 9, a ~ z,+,C, M , (, ), &, ? , ? (period), and , (comma) are usable.
? 1997 mitsubishi electric corp. ki-9711 printed in japan (rod) ii new publication, effective nov. 1997. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. mitsubishi microcomputers 7480/7481 group single-chip 8-bit cmos microcomputer preliminar y notice: this is not a final specification. some parametric limits are subject to change.
rev. rev. no. date 1.0 first edition 971130 revision description list 7480/7481 group data sheet (1/1) revision description

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